nds_test2
diff src/startup/arm9entry.s @ 0:abcaf667f2bd
initial commit (3d + 2d)
author | John Tsiombikas <nuclear@member.fsf.org> |
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date | Sun, 28 Jan 2018 20:05:26 +0200 |
parents | |
children |
line diff
1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 1.2 +++ b/src/startup/arm9entry.s Sun Jan 28 20:05:26 2018 +0200 1.3 @@ -0,0 +1,192 @@ 1.4 +@ vi:set filetype=armasm: 1.5 + .arch armv5te 1.6 + .cpu arm946e-s 1.7 + .section ".crt0","ax" 1.8 + .global _start 1.9 + .align 4 1.10 + .arm 1.11 +_start: 1.12 + mov r0, #0x04000000 @ IME = 0; 1.13 + str r0, [r0, #0x208] 1.14 + 1.15 + @ set sensible stacks to allow bios call 1.16 + 1.17 + mov r0, #0x13 @ Switch to SVC Mode 1.18 + msr cpsr, r0 1.19 + mov r1,#0x03000000 1.20 + sub r1,r1,#0x1000 1.21 + mov sp,r1 1.22 + mov r0, #0x1F @ Switch to System Mode 1.23 + msr cpsr, r0 1.24 + sub r1,r1,#0x100 1.25 + mov sp,r1 1.26 + 1.27 + ldr r3, =mpu_setup 1.28 + blx r3 1.29 + 1.30 + mov r0, #0x12 @ Switch to IRQ Mode 1.31 + msr cpsr, r0 1.32 + ldr sp, =__sp_irq @ Set IRQ stack 1.33 + 1.34 + mov r0, #0x13 @ Switch to SVC Mode 1.35 + msr cpsr, r0 1.36 + ldr sp, =__sp_svc @ Set SVC stack 1.37 + 1.38 + mov r0, #0x1F @ Switch to System Mode 1.39 + msr cpsr, r0 1.40 + ldr sp, =__sp_usr @ Set user stack 1.41 + 1.42 + mov r12, #0x4000000 @ Read system ROM status (NTR/TWL) 1.43 + ldrb r11, [r12,r12,lsr #12] 1.44 + and r11, r11, #0x3 1.45 + 1.46 + b skip_sync 1.47 + 1.48 + mov r9, #(0x0<<8) @ Synchronize with ARM7 1.49 + str r9, [r12, #0x180] 1.50 + mov r9, #0x9 1.51 + bl IPCSync 1.52 + mov r9, #(0xA<<8) 1.53 + str r9, [r12, #0x180] 1.54 + mov r9, #0xB 1.55 + bl IPCSync 1.56 + mov r9, #(0xC<<8) 1.57 + str r9, [r12, #0x180] 1.58 + mov r9, #0xD 1.59 + bl IPCSync 1.60 + mov r9, r11, lsl #8 1.61 + str r9, [r12, #0x180] 1.62 + mov r9, #0 1.63 + bl IPCSync 1.64 + str r9, [r12, #0x180] 1.65 + 1.66 +skip_sync: 1.67 + 1.68 + ldr r1, =__itcm_lma @ Copy instruction tightly coupled memory (itcm section) from LMA to VMA 1.69 + ldr r2, =__itcm_start 1.70 + ldr r4, =__itcm_end 1.71 + bl CopyMemCheck 1.72 + 1.73 + ldr r1, =__vectors_lma @ Copy reserved vectors area (itcm section) from LMA to VMA 1.74 + ldr r2, =__vectors_start 1.75 + ldr r4, =__vectors_end 1.76 + bl CopyMemCheck 1.77 + 1.78 + ldr r1, =__dtcm_lma @ Copy data tightly coupled memory (dtcm section) from LMA to VMA 1.79 + ldr r2, =__dtcm_start 1.80 + ldr r4, =__dtcm_end 1.81 + bl CopyMemCheck 1.82 + 1.83 + cmp r11, #1 1.84 + ldrne r10, =__end__ @ (DS mode) heap start 1.85 + ldreq r10, =__twl_end__ @ (DSi mode) heap start 1.86 + 1.87 + ldr r0, =__bss_start__ @ Clear BSS section 1.88 + ldr r1, =__bss_end__ 1.89 + sub r1, r1, r0 1.90 + bl ClearMem 1.91 + 1.92 + ldr r0, =__sbss_start @ Clear SBSS section 1.93 + ldr r1, =__sbss_end 1.94 + sub r1, r1, r0 1.95 + bl ClearMem 1.96 + 1.97 + cmp r11, #1 1.98 + bne NotTWL 1.99 + ldr r9, =__dsimode @ set DSi mode flag 1.100 + strb r11, [r9] 1.101 + 1.102 + @ Copy TWL area (arm9i section) from LMA to VMA 1.103 + ldr r1, =0x02ffe1c8 @ Get ARM9i LMA from header 1.104 + ldr r1, [r1] 1.105 + 1.106 + ldr r2, =__arm9i_start__ 1.107 + cmp r1, r2 @ skip copy if LMA=VMA 1.108 + ldrne r4, =__arm9i_end__ 1.109 + blne CopyMemCheck 1.110 + 1.111 + ldr r0, =__twl_bss_start__ @ Clear TWL BSS section 1.112 + ldr r1, =__twl_bss_end__ 1.113 + sub r1, r1, r0 1.114 + bl ClearMem 1.115 + 1.116 +NotTWL: 1.117 + ldr r0, =__secure_area__ 1.118 + ldr r3, =main 1.119 + bx r3 @ jump to user code 1.120 +infloop: 1.121 + b infloop 1.122 + 1.123 + 1.124 + 1.125 +@--------------------------------------------------------------------------------- 1.126 +@ Clear memory to 0x00 if length != 0 1.127 +@ r0 = Start Address 1.128 +@ r1 = Length 1.129 +@--------------------------------------------------------------------------------- 1.130 +ClearMem: 1.131 +@--------------------------------------------------------------------------------- 1.132 + mov r2, #3 @ Round down to nearest word boundary 1.133 + add r1, r1, r2 @ Shouldn't be needed 1.134 + bics r1, r1, r2 @ Clear 2 LSB (and set Z) 1.135 + bxeq lr @ Quit if copy size is 0 1.136 + 1.137 + mov r2, #0 1.138 +ClrLoop: 1.139 + stmia r0!, {r2} 1.140 + subs r1, r1, #4 1.141 + bne ClrLoop 1.142 + 1.143 + bx lr 1.144 + 1.145 +@--------------------------------------------------------------------------------- 1.146 +@ Copy memory if length != 0 1.147 +@ r1 = Source Address 1.148 +@ r2 = Dest Address 1.149 +@ r4 = Dest Address + Length 1.150 +@--------------------------------------------------------------------------------- 1.151 +CopyMemCheck: 1.152 +@--------------------------------------------------------------------------------- 1.153 + sub r3, r4, r2 @ Is there any data to copy? 1.154 +@--------------------------------------------------------------------------------- 1.155 +@ Copy memory 1.156 +@ r1 = Source Address 1.157 +@ r2 = Dest Address 1.158 +@ r3 = Length 1.159 +@--------------------------------------------------------------------------------- 1.160 +CopyMem: 1.161 +@--------------------------------------------------------------------------------- 1.162 + mov r0, #3 @ These commands are used in cases where 1.163 + add r3, r3, r0 @ the length is not a multiple of 4, 1.164 + bics r3, r3, r0 @ even though it should be. 1.165 + bxeq lr @ Length is zero, so exit 1.166 +CIDLoop: 1.167 + ldmia r1!, {r0} 1.168 + stmia r2!, {r0} 1.169 + subs r3, r3, #4 1.170 + bne CIDLoop 1.171 + 1.172 + bx lr 1.173 + 1.174 +@ Synchronize with ARM7 1.175 +IPCSync: 1.176 + ldr r10, [r12, #0x180] 1.177 + and r10, r10, #0xF 1.178 + cmp r10, r9 1.179 + bne IPCSync 1.180 + bx lr 1.181 + 1.182 + 1.183 + .align 1.184 + .pool 1.185 + 1.186 + .data 1.187 + .global __dsimode 1.188 +__dsimode: 1.189 + .word 0 1.190 + 1.191 + .section ".secure","a" 1.192 + .align 2 1.193 + .global __secure_area__ 1.194 +__secure_area__: 1.195 + .space 2048, 0