nds_test2
changeset 0:abcaf667f2bd
initial commit (3d + 2d)
| author | John Tsiombikas <nuclear@member.fsf.org> |
|---|---|
| date | Sun, 28 Jan 2018 20:05:26 +0200 |
| parents | |
| children | d625ba001a62 |
| files | .hgignore Makefile data/icon.bmp.base64 src/arm7/main.c src/ds3.c src/ds3.h src/dsregs.h src/main.c src/startup/arm7entry.s src/startup/arm9entry.s src/startup/mpu_setup.S |
| diffstat | 11 files changed, 1304 insertions(+), 0 deletions(-) [+] |
line diff
1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 1.2 +++ b/.hgignore Sun Jan 28 20:05:26 2018 +0200 1.3 @@ -0,0 +1,7 @@ 1.4 +\.o$ 1.5 +\.d$ 1.6 +\.swp$ 1.7 +\.elf$ 1.8 +\.bin$ 1.9 +\.nds$ 1.10 +\.bmp$
2.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 2.2 +++ b/Makefile Sun Jan 28 20:05:26 2018 +0200 2.3 @@ -0,0 +1,45 @@ 2.4 +csrc = $(wildcard src/*.c) 2.5 +ssrc = src/startup/arm9entry.s $(wildcard src/*.s) 2.6 +Ssrc = $(wildcard src/startup/*.S) $(wildcard src/*.S) 2.7 +obj = $(csrc:.c=.o) $(ssrc:.s=.o) $(Ssrc:.S=.o) 2.8 + 2.9 +csrc-arm7 = $(wildcard src/arm7/*.c) 2.10 +ssrc-arm7 = src/startup/arm7entry.s $(wildcard src/arm7/*.s) 2.11 +obj-arm7 = $(csrc-arm7:.c=.o) $(ssrc-arm7:.s=.o) 2.12 + 2.13 +name = test2 2.14 +bin = $(name).nds 2.15 + 2.16 +ARCH = arm-none-eabi- 2.17 +CPP = $(ARCH)cpp 2.18 +CC = $(ARCH)gcc 2.19 +AS = $(ARCH)as 2.20 +OBJCOPY = $(ARCH)objcopy 2.21 + 2.22 +EMU = desmume-cli 2.23 + 2.24 +opt = -O3 -fomit-frame-pointer -mcpu=arm946e-s -mtune=arm946e-s 2.25 +dbg = -g 2.26 + 2.27 +CFLAGS = -mthumb $(opt) $(dbg) 2.28 +LDFLAGS = -nostartfiles -Wl,--gc-sections -lm 2.29 + 2.30 +$(bin): arm9.elf arm7.elf data/icon.bmp 2.31 + ndstool -c $@ -9 arm9.elf -7 arm7.elf -b data/icon.bmp "$(name);mindlapse" 2.32 + 2.33 +arm9.elf: $(obj) 2.34 + $(CC) -o $@ $(obj) -Wl,-T,ds_arm9.mem -Wl,-T,ds_arm9.ld $(LDFLAGS) 2.35 + 2.36 +arm7.elf: $(obj-arm7) 2.37 + $(CC) -o $@ $(obj-arm7) -Wl,-T,ds_arm7.ld $(LDFLAGS) 2.38 + 2.39 +.PHONY: clean 2.40 +clean: 2.41 + rm -f $(obj) $(obj-arm7) $(bin) arm9.elf arm7.elf $(dep) 2.42 + 2.43 +.PHONY: simrun 2.44 +simrun: $(bin) 2.45 + $(EMU) $(EMUFLAGS) $(bin) 2.46 + 2.47 +data/icon.bmp: data/icon.bmp.base64 2.48 + base64 -d $< >$@
3.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 3.2 +++ b/data/icon.bmp.base64 Sun Jan 28 20:05:26 2018 +0200 3.3 @@ -0,0 +1,37 @@ 3.4 +Qk02CAAAAAAAADYEAAAoAAAAIAAAACAAAAABAAgAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAb29h 3.5 +AFBHQgBgW1IAen9pAIWNbgCOk30Al6R7AKGmjACjt3cArraTAL3AoQA3KCgARDQ2AMa9twAfExYA 3.6 +2c/NAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBv 3.7 +b2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9v 3.8 +YQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29h 3.9 +AG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EA 3.10 +b29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBv 3.11 +b2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9v 3.12 +YQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29h 3.13 +AG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EA 3.14 +b29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBv 3.15 +b2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9v 3.16 +YQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29h 3.17 +AG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EA 3.18 +b29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBv 3.19 +b2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9v 3.20 +YQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29h 3.21 +AG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EA 3.22 +b29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAA4ODg4O 3.23 +Dg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4O 3.24 +Dg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4O 3.25 +Dg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4O 3.26 +Dg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODgsLDg4ODg4ODg4ODg4ODg4O 3.27 +Dg4ODg4ODg4ODg4ODg4LDgsODg4ODg4ODg4ODg4ODg4ODg4ODgsLDg4ODgsODg4ODg4ODg4ODg4O 3.28 +AgADAwAAAg4ODgEDDQAODgIDBQMDAgIAAAUFBAwODg4FBwMEBwYHAAQFBwoPAg4LAQcDAwQHAgUD 3.29 +BAMLDg4OCwUFDg4LAgcABAIHBQcCDg4OCw4OAAcBCw4ODg4ODgsMBQULCw4OAAQOAAcLBwMHBQUE 3.30 +BQcHAAsFBwAODg4ODAEFBQEMDg4CBwMHAA4GAgAACQkAAQ4ODAELDg4ODg4BAgcNAAELDgMPCQQO 3.31 +CwUFAwMHCgUDAwAFAAAABQEODgECDQ8CDAsOAg0JAgAFBQUFAwAABAUEBQgFAwMCDg4ODAIPBwsB 3.32 +Ag4CBwAOBwcOAgcADg4ODgIECAkFAQ4ODg4LAQcEDgMFDgIHDg4EBA4BBQAODg4BBQQABQcJAg4O 3.33 +Dg4LBQUOAwcOAgcODgUEDgEDAg4OAQMFAQ4MAQUHAQ4ODg4FBQAFCQMCBw4OBAUOAQMCDgwFBQEL 3.34 +CwsBAQUADg4ODgUFBwcHCgQFCw4EBw4BBAMBAwMCDAwBAQsFBQEODg4OAwkFAgIHCgULDgcDDgEE 3.35 +CQkFAgsCAQICAwUADg4ODg4FBwAODgIHBQEOBgUMAQQGAwELAgQHBQUFAg4ODg4ODgQCDg4ODgEA 3.36 +DA4DAgsABQIMDgIHBwQAAAELDg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODgsMAQIBDAsODg4ODg4O 3.37 +Dg4ODg4ODg4ODg4ODg4ODg4ODgsMDAsLDg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4O 3.38 +Dg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4O 3.39 +Dg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4O 3.40 +Dg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4=
4.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 4.2 +++ b/src/arm7/main.c Sun Jan 28 20:05:26 2018 +0200 4.3 @@ -0,0 +1,4 @@ 4.4 +int main(void) 4.5 +{ 4.6 + for(;;); 4.7 +}
5.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 5.2 +++ b/src/ds3.c Sun Jan 28 20:05:26 2018 +0200 5.3 @@ -0,0 +1,108 @@ 5.4 +#include <stdint.h> 5.5 +#include "dsregs.h" 5.6 +#include "ds3.h" 5.7 + 5.8 +void ds3_enable(unsigned int x) 5.9 +{ 5.10 + REG_DISP3DCNT |= x; 5.11 +} 5.12 + 5.13 +void ds3_disable(unsigned int x) 5.14 +{ 5.15 + REG_DISP3DCNT &= ~x; 5.16 +} 5.17 + 5.18 +void ds3_clear_color(uint16_t color, int a) 5.19 +{ 5.20 + REG_CLEAR_COLOR = color | ((a & 0x1f) << 16); 5.21 +} 5.22 + 5.23 +void ds3_clear_depth(int z) 5.24 +{ 5.25 + REG_CLEAR_DEPTH = z; 5.26 +} 5.27 + 5.28 +void ds3_viewport(int x, int y, int w, int h) 5.29 +{ 5.30 + int x1 = x + w - 1; 5.31 + int y1 = y + h - 1; 5.32 + 5.33 + if(x1 > 255) x1 = 255; 5.34 + if(y1 > 191) y1 = 191; 5.35 + 5.36 + REG_VIEWPORT = x | (y << 8) | (x1 << 16) | (y1 << 24); 5.37 +} 5.38 + 5.39 +void ds3_matrix_mode(int mmode) 5.40 +{ 5.41 + REG_MTX_MODE = mmode; 5.42 +} 5.43 + 5.44 +void ds3_load_identity(void) 5.45 +{ 5.46 + REG_MTX_IDENTITY = 0; 5.47 +} 5.48 + 5.49 +void ds3_load_matrix(int32_t *m) 5.50 +{ 5.51 + int i; 5.52 + for(i=0; i<16; i++) { 5.53 + int16_t val = (int16_t)(*m++ >> 4); 5.54 + REG_MTX_LOAD_4X4 = val; 5.55 + } 5.56 +} 5.57 + 5.58 +void ds3_push_matrix(void) 5.59 +{ 5.60 + REG_MTX_PUSH = 0; 5.61 +} 5.62 + 5.63 +void ds3_pop_matrix(void) 5.64 +{ 5.65 + REG_MTX_POP = 1; 5.66 +} 5.67 + 5.68 +void ds3_translate(int32_t x, int32_t y, int32_t z) 5.69 +{ 5.70 + REG_MTX_TRANS = (int16_t)(x >> 4); 5.71 + REG_MTX_TRANS = (int16_t)(y >> 4); 5.72 + REG_MTX_TRANS = (int16_t)(z >> 4); 5.73 +} 5.74 + 5.75 +void ds3_scale(int32_t x, int32_t y, int32_t z) 5.76 +{ 5.77 + REG_MTX_SCALE = (int16_t)(x >> 4); 5.78 + REG_MTX_SCALE = (int16_t)(y >> 4); 5.79 + REG_MTX_SCALE = (int16_t)(z >> 4); 5.80 +} 5.81 + 5.82 +void ds3_swap_buffers(void) 5.83 +{ 5.84 + REG_SWAP_BUFFERS = 0; 5.85 +} 5.86 + 5.87 +void ds3_begin(int prim) 5.88 +{ 5.89 + REG_BEGIN_VTXS = prim; 5.90 +} 5.91 + 5.92 +void ds3_end(void) 5.93 +{ 5.94 + REG_END_VTXS = 0; 5.95 +} 5.96 + 5.97 +void ds3_vertex3(int32_t x, int32_t y, int32_t z) 5.98 +{ 5.99 + REG_VTX_16 = ((x >> 4) & 0xffff) | ((y << 12) & 0xffff0000); 5.100 + REG_VTX_16 = (z >> 4) & 0xffff; 5.101 +} 5.102 + 5.103 +void ds3_color(uint16_t color) 5.104 +{ 5.105 + REG_COLOR = color; 5.106 +} 5.107 + 5.108 +void ds3_color3b(unsigned char r, unsigned char g, unsigned char b) 5.109 +{ 5.110 + REG_COLOR = RGB15(r >> 3, g >> 3, b >> 3); 5.111 +}
6.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 6.2 +++ b/src/ds3.h Sun Jan 28 20:05:26 2018 +0200 6.3 @@ -0,0 +1,52 @@ 6.4 +#ifndef DS3_H_ 6.5 +#define DS3_H_ 6.6 + 6.7 +#include <stdint.h> 6.8 + 6.9 +#define RGB15(r, g, b) (((r) & 0x1f) | (((g) & 0x1f) << 5) | (((b) & 0x1f) << 10)) 6.10 + 6.11 +#define DS3_TEXTURE_2D 0x0001 6.12 +#define DS3_SPECULAR 0x0002 6.13 +#define DS3_ALPHA_TEST 0x0004 6.14 +#define DS3_BLEND 0x0008 6.15 +#define DS3_ANTIALIAS 0x0010 6.16 +#define DS3_EDGE 0x0020 6.17 +#define DS3_FOG_ALPHA 0x0040 6.18 +#define DS3_FOG 0x0080 6.19 +#define DS3_CLEAR_BM 0x4000 6.20 + 6.21 +#define DS3_TRIANGLES 0 6.22 +#define DS3_QUADS 1 6.23 +#define DS3_TRIANGLE_STRIP 2 6.24 +#define DS3_QUAD_STRIP 3 6.25 + 6.26 +#define DS3_PROJECTION 0 6.27 +#define DS3_MODELVIEW 1 6.28 +#define DS3_TEXTURE 2 6.29 + 6.30 +void ds3_enable(unsigned int x); 6.31 +void ds3_disable(unsigned int x); 6.32 + 6.33 +void ds3_clear_color(uint16_t color, int a); 6.34 +void ds3_clear_depth(int z); 6.35 + 6.36 +void ds3_viewport(int x, int y, int w, int h); 6.37 + 6.38 +void ds3_matrix_mode(int mmode); 6.39 +void ds3_load_identity(void); 6.40 +void ds3_load_matrix(int32_t *m); 6.41 +void ds3_push_matrix(void); 6.42 +void ds3_pop_matrix(void); 6.43 +void ds3_translate(int32_t x, int32_t y, int32_t z); 6.44 +void ds3_scale(int32_t x, int32_t y, int32_t z); 6.45 + 6.46 +void ds3_swap_buffers(void); 6.47 + 6.48 +void ds3_begin(int prim); 6.49 +void ds3_end(void); 6.50 + 6.51 +void ds3_vertex3(int32_t x, int32_t y, int32_t z); 6.52 +void ds3_color(uint16_t color); 6.53 +void ds3_color3b(unsigned char r, unsigned char g, unsigned char b); 6.54 + 6.55 +#endif /* DS3_H_ */
7.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 7.2 +++ b/src/dsregs.h Sun Jan 28 20:05:26 2018 +0200 7.3 @@ -0,0 +1,360 @@ 7.4 +#ifndef DSREGS_H_ 7.5 +#define DSREGS_H_ 7.6 + 7.7 +#include <stdint.h> 7.8 + 7.9 +#define REG_BASE 0x4000000 7.10 +#define REG8(x) (*(volatile int8_t*)(REG_BASE + (x))) 7.11 +#define REG16(x) (*(volatile int16_t*)(REG_BASE + (x))) 7.12 +#define REG32(x) (*(volatile int32_t*)(REG_BASE + (x))) 7.13 +#define REG64(x) (*(volatile int64_t*)(REG_BASE + (x))) 7.14 + 7.15 +/* ---- display engine A ---- */ 7.16 +#define REG_DISPCNT REG32(0x00) 7.17 +#define REG_DISPSTAT REG16(0x04) 7.18 +#define REG_VCOUNT REG16(0x06) 7.19 +#define REG_BG0CNT REG16(0x08) 7.20 +#define REG_BG1CNT REG16(0x0a) 7.21 +#define REG_BG2CNT REG16(0x0c) 7.22 +#define REG_BG3CNT REG16(0x0e) 7.23 +/* scrolling registers */ 7.24 +#define REG_BG0HOFS REG16(0x10) 7.25 +#define REG_BG0VOFS REG16(0x12) 7.26 +#define REG_BG1HOFS REG16(0x14) 7.27 +#define REG_BG1VOFS REG16(0x16) 7.28 +#define REG_BG2HOFS REG16(0x18) 7.29 +#define REG_BG2VOFS REG16(0x1a) 7.30 +#define REG_BG3HOFS REG16(0x1c) 7.31 +#define REG_BG3VOFS REG16(0x1e) 7.32 +/* BG rotation and scaling registers */ 7.33 +#define REG_BG2PA REG16(0x20) 7.34 +#define REG_BG2PB REG16(0x22) 7.35 +#define REG_BG2PC REG16(0x24) 7.36 +#define REG_BG2PD REG16(0x26) 7.37 +#define REG_BG2X REG32(0x28) 7.38 +#define REG_BG2Y REG32(0x2c) 7.39 +#define REG_BG3PA REG16(0x30) 7.40 +#define REG_BG3PB REG16(0x32) 7.41 +#define REG_BG3PC REG16(0x34) 7.42 +#define REG_BG3PD REG16(0x36) 7.43 +#define REG_BG3X REG32(0x38) 7.44 +#define REG_BG3Y REG32(0x3c) 7.45 +/* window registers */ 7.46 +#define REG_WIN0H REG16(0x40) 7.47 +#define REG_WIN1H REG16(0x42) 7.48 +#define REG_WIN0V REG16(0x44) 7.49 +#define REG_WIN1V REG16(0x46) 7.50 +#define REG_WININ REG16(0x48) 7.51 +#define REG_WINOUT REG16(0x4a) 7.52 +/* mosaic */ 7.53 +#define REG_MOSAIC REG16(0x4c) 7.54 +/* color effects */ 7.55 +#define REG_BLDCNT REG16(0x50) 7.56 +#define REG_BLDALPHA REG16(0x52) 7.57 +#define REG_BLDY REG16(0x54) 7.58 + 7.59 +#define REG_DISP3DCNT REG16(0x60) 7.60 +#define REG_DISPCAPCNT REG32(0x64) 7.61 +#define REG_DISP_MMEM_FIFO REG32(0x68) 7.62 +#define REG_MASTER_BRIGHT REG16(0x6c) 7.63 + 7.64 +/* ---- display engine B ---- */ 7.65 +#define REG_B_DISPCNT REG32(0x1000) 7.66 +#define REG_B_BG0CNT REG16(0x1008) 7.67 +#define REG_B_BG1CNT REG16(0x100a) 7.68 +#define REG_B_BG2CNT REG16(0x100c) 7.69 +#define REG_B_BG3CNT REG16(0x100e) 7.70 +/* scrolling registers */ 7.71 +#define REG_B_BG0HOFS REG16(0x1010) 7.72 +#define REG_B_BG0VOFS REG16(0x1012) 7.73 +#define REG_B_BG1HOFS REG16(0x1014) 7.74 +#define REG_B_BG1VOFS REG16(0x1016) 7.75 +#define REG_B_BG2HOFS REG16(0x1018) 7.76 +#define REG_B_BG2VOFS REG16(0x101a) 7.77 +#define REG_B_BG3HOFS REG16(0x101c) 7.78 +#define REG_B_BG3VOFS REG16(0x101e) 7.79 +/* BG rotation and scaling registers */ 7.80 +#define REG_B_BG2PA REG16(0x1020) 7.81 +#define REG_B_BG2PB REG16(0x1022) 7.82 +#define REG_B_BG2PC REG16(0x1024) 7.83 +#define REG_B_BG2PD REG16(0x1026) 7.84 +#define REG_B_BG2X REG32(0x1028) 7.85 +#define REG_B_BG2Y REG32(0x102c) 7.86 +#define REG_B_BG3PA REG16(0x1030) 7.87 +#define REG_B_BG3PB REG16(0x1032) 7.88 +#define REG_B_BG3PC REG16(0x1034) 7.89 +#define REG_B_BG3PD REG16(0x1036) 7.90 +#define REG_B_BG3X REG32(0x1038) 7.91 +#define REG_B_BG3Y REG32(0x103c) 7.92 +/* window registers */ 7.93 +#define REG_B_WIN0H REG16(0x1040) 7.94 +#define REG_B_WIN1H REG16(0x1042) 7.95 +#define REG_B_WIN0V REG16(0x1044) 7.96 +#define REG_B_WIN1V REG16(0x1046) 7.97 +#define REG_B_WININ REG16(0x1048) 7.98 +#define REG_B_WINOUT REG16(0x104a) 7.99 +/* mosaic */ 7.100 +#define REG_B_MOSAIC REG16(0x104c) 7.101 +/* color effects */ 7.102 +#define REG_B_BLDCNT REG16(0x1050) 7.103 +#define REG_B_BLDALPHA REG16(0x1052) 7.104 +#define REG_B_BLDY REG16(0x1054) 7.105 + 7.106 +#define REG_B_MASTER_BRIGHT REG16(0x106c) 7.107 + 7.108 + 7.109 +#define DISPCNT_BGMODE(x) (x) 7.110 +#define DISPCNT_MODE(x) ((uint32_t)(x) << 16) 7.111 +#define DISPCNT_BG0_3D 0x00000008 7.112 +#define DISPCNT_TILE_OBJ_1DMAP 0x00000010 7.113 +#define DISPCNT_BM_OBJ_256X256 0x00000020 7.114 +#define DISPCNT_BM_OBJ_1DMAP 0x00000040 7.115 +#define DISPCNT_BLANK 0x00000080 7.116 +#define DISPCNT_BG0 0x00000100 7.117 +#define DISPCNT_BG1 0x00000200 7.118 +#define DISPCNT_BG2 0x00000400 7.119 +#define DISPCNT_BG3 0x00000800 7.120 +#define DISPCNT_OBJ 0x00001000 7.121 +#define DISPCNT_WIN0 0x00002000 7.122 +#define DISPCNT_WIN1 0x00004000 7.123 +#define DISPCNT_OBJWIN 0x00008000 7.124 + 7.125 +#define BGXCNT_PRIO(x) (x) 7.126 +#define BGXCNT_CHARBASE(x) ((x) << 2) 7.127 +#define BGXCNT_MOSAIC 0x0040 7.128 +#define BGXCNT_COL_256 0x0080 7.129 +#define BGXCNT_BM 0x0080 7.130 +#define BGXCNT_SCRBASE(x) ((x) << 8) 7.131 +#define BGXCNT_OVF_WRAP 0x2000 7.132 +#define BGXCNT_SCRSIZE(x) ((x) << 14) 7.133 +#define BGXCNT_TX_256X256 BGXCNT_SCRSIZE(0) 7.134 +#define BGXCNT_TX_512X256 BGXCNT_SCRSIZE(1) 7.135 +#define BGXCNT_TX_256X512 BGXCNT_SCRSIZE(2) 7.136 +#define BGXCNT_TX_512X512 BGXCNT_SCRSIZE(3) 7.137 +#define BGXCNT_RS_128X128 BGXCNT_SCRSIZE(0) 7.138 +#define BGXCNT_RS_256X256 BGXCNT_SCRSIZE(1) 7.139 +#define BGXCNT_RS_512X512 BGXCNT_SCRSIZE(2) 7.140 +#define BGXCNT_RS_1024X1024 BGXCNT_SCRSIZE(3) 7.141 +#define BGXCNT_BM_128X128 (BGXCNT_SCRSIZE(0) | BGXCNT_BM) 7.142 +#define BGXCNT_BM_256X256 (BGXCNT_SCRSIZE(1) | BGXCNT_BM) 7.143 +#define BGXCNT_BM_512X256 (BGXCNT_SCRSIZE(2) | BGXCNT_BM) 7.144 +#define BGXCNT_BM_512X512 (BGXCNT_SCRSIZE(3) | BGXCNT_BM) 7.145 +#define BGXCNT_BM8 0 7.146 +#define BGXCNT_BM16 0x0004 7.147 + 7.148 +#define VRAM_OFFSET(x) ((x) << 3) 7.149 +#define VRAM_ENABLE 0x80 7.150 + 7.151 +/* ---- DMA registers ---- */ 7.152 +#define REG_DMA0SAD REG32(0xb0) 7.153 +#define REG_DMA0DAD REG32(0xb4) 7.154 +#define REG_DMA0CNT_L REG16(0xb8) 7.155 +#define REG_DMA0CNT_H REG16(0xba) 7.156 +#define REG_DMA1SAD REG32(0xbc) 7.157 +#define REG_DMA1DAD REG32(0xc0) 7.158 +#define REG_DMA1CNT_L REG16(0xc4) 7.159 +#define REG_DMA1CNT_H REG16(0xc6) 7.160 +#define REG_DMA2SAD REG32(0xc8) 7.161 +#define REG_DMA2DAD REG32(0xcc) 7.162 +#define REG_DMA2CNT_L REG16(0xd0) 7.163 +#define REG_DMA2CNT_H REG16(0xd2) 7.164 +#define REG_DMA3SAD REG32(0xd4) 7.165 +#define REG_DMA3DAD REG32(0xd8) 7.166 +#define REG_DMA3CNT_L REG16(0xdc) 7.167 +#define REG_DMA3CNT_H REG16(0xde) 7.168 +#define REG_DMA0FILL REG32(0xe0) 7.169 +#define REG_DMA1FILL REG32(0xe4) 7.170 +#define REG_DMA2FILL REG32(0xe8) 7.171 +#define REG_DMA3FILL REG32(0xec) 7.172 + 7.173 +/* ---- timer registers ---- */ 7.174 +#define REG_TM0CNT_L REG16(0x100) 7.175 +#define REG_TM0CNT_H REG16(0x102) 7.176 +#define REG_TM1CNT_L REG16(0x104) 7.177 +#define REG_TM1CNT_H REG16(0x106) 7.178 +#define REG_TM2CNT_L REG16(0x108) 7.179 +#define REG_TM2CNT_H REG16(0x10a) 7.180 +#define REG_TM3CNT_L REG16(0x10c) 7.181 +#define REG_TM3CNT_H REG16(0x10e) 7.182 + 7.183 +/* ---- keypad registers ---- */ 7.184 +#define REG_KEYINPUT REG16(0x130) 7.185 +#define REG_KEYCNT REG16(0x132) 7.186 + 7.187 +/* ---- IPC/ROM registers ---- */ 7.188 +#define REG_IPCSYNC REG16(0x180) 7.189 +#define REG_IPCFIFOCNT REG16(0x184) 7.190 +#define REG_IPCFIFOSEND REG32(0x188) 7.191 +#define REG_AUXSPICNT REG16(0x1a0) 7.192 +#define REG_AUXSPIDATA REG16(0x1a2) 7.193 +#define REG_GCARDCNT REG32(0x1a4) 7.194 +#define REG_GCARDCMD64 REG64(0x1a8) 7.195 +#define REG_GCARDSEED0 REG32(0x1b0) 7.196 +#define REG_GCARDSEED1 REG32(0x1b4) 7.197 +#define REG_GCARDSEED0X REG16(0x1b8) 7.198 +#define REG_GCARDSEED1X REG16(0x1ba) 7.199 + 7.200 +/* ---- memory & IRQ control registers ---- */ 7.201 +#define REG_EXMEMCNT REG16(0x204) 7.202 +#define REG_IME REG16(0x208) 7.203 +#define REG_IE REG32(0x210) 7.204 +#define REG_IF REG32(0x214) 7.205 +#define REG_VRAMCNT_A REG8(0x240) 7.206 +#define REG_VRAMCNT_B REG8(0x241) 7.207 +#define REG_VRAMCNT_C REG8(0x242) 7.208 +#define REG_VRAMCNT_D REG8(0x243) 7.209 +#define REG_VRAMCNT_E REG8(0x244) 7.210 +#define REG_VRAMCNT_F REG8(0x245) 7.211 +#define REG_VRAMCNT_G REG8(0x246) 7.212 +#define REG_WRAMCNT REG8(0x247) 7.213 +#define REG_VRAMCNT_H REG8(0x248) 7.214 +#define REG_VRAMCNT_I REG8(0x249) 7.215 + 7.216 +/* ---- math hardware registers ---- */ 7.217 +#define REG_DIVCNT REG16(0x280) 7.218 +#define REG_DIV_NUMER REG64(0x290) 7.219 +#define REG_DIV_DENOM REG64(0x298) 7.220 +#define REG_DIV_RESULT REG64(0x2a0) 7.221 +#define REG_DIVREM_RESULT REG64(0x2a8) 7.222 +#define REG_SQRTCNT REG16(0x2b0) 7.223 +#define REG_SQRT_RESULT REG32(0x2b4) 7.224 +#define REG_SQRT_PARAM REG64(0x2b8) 7.225 +#define REG_POSTFLG REG32(0x300) 7.226 +#define REG_POWCNT1 REG16(0x304) 7.227 +#define REG_POWCNT2 REG16(0x304) 7.228 + 7.229 +#define POWCNT1_LCD 0x0001 7.230 +#define POWCNT1_2DA 0x0002 7.231 +#define POWCNT1_3DREND 0x0004 7.232 +#define POWCNT1_3DGEOM 0x0008 7.233 +#define POWCNT1_2DB 0x0200 7.234 +#define POWCNT1_DSWAP 0x8000 7.235 + 7.236 +#define POWCNT2_SOUND 0x0001 7.237 +#define POWCNT2_WIFI 0x0002 7.238 + 7.239 +/* ---- sound registers ---- */ 7.240 +#define REG_SOUNDXCNT(x) REG32(0x400 | ((x) << 4)) 7.241 +#define REG_SOUNDXSAD(x) REG32(0x404 | ((x) << 4)) 7.242 +#define REG_SOUNDXTMR(x) REG32(0x408 | ((x) << 4)) 7.243 +#define REG_SOUNDXPNT(x) REG32(0x40a | ((x) << 4)) 7.244 +#define REG_SOUNDXLEN(x) REG32(0x40c | ((x) << 4)) 7.245 +#define REG_SOUNDCNT REG32(0x500) 7.246 +#define REG_SOUNDBIAS REG32(0x504) 7.247 + 7.248 +/* ---- 3D hardware registers ---- */ 7.249 +/* rendering engine */ 7.250 +#define REG_RDLINES_COUNR REG8(0x320) 7.251 +#define REG_EDGE_COLOR0 REG16(0x330) 7.252 +#define REG_EDGE_COLOR1 REG16(0x332) 7.253 +#define REG_EDGE_COLOR2 REG16(0x334) 7.254 +#define REG_EDGE_COLOR3 REG16(0x336) 7.255 +#define REG_EDGE_COLOR4 REG16(0x338) 7.256 +#define REG_EDGE_COLOR5 REG16(0x33a) 7.257 +#define REG_EDGE_COLOR6 REG16(0x33c) 7.258 +#define REG_EDGE_COLOR7 REG16(0x33e) 7.259 +#define REG_ALPHA_TEST_REF REG8(0x340) 7.260 +#define REG_CLEAR_COLOR REG32(0x350) 7.261 +#define REG_CLEAR_DEPTH REG16(0x354) 7.262 +#define REG_CLRIMAGE_OFFSET REG16(0x356) 7.263 +#define REG_FOG_COLOR REG32(0x358) 7.264 +#define REG_FOG_OFFSET REG16(0x35c) 7.265 +#define FOG_TABLE_ADDR ((uint8_t*)(REG_BASE + 0x360)) 7.266 +#define TOON_TABLE_ADDR ((uint16_t*)(REG_BASE + 0x380)) 7.267 +/* geometry engine */ 7.268 +#define GXFIFO_ADDR ((uint8_t*)(REG_BASE + 0x400)) 7.269 +#define REG_GXSTAT REG32(0x600) 7.270 +#define REG_RAM_COUNT REG32(0x604) 7.271 +#define REG_DISP_1DOT_DEPTH REG16(0x610) 7.272 +#define POS_RESULT_ADDR ((uint8_t*)(REG_BASE + 0x620)) 7.273 +#define VEC_RESULT_ADDR ((uint8_t*)(REG_BASE + 0x630)) 7.274 +#define CLIPMTX_RESULT_ADDR ((uint32_t*)(REG_BASE + 0x640)) 7.275 +#define VECMTX_RESULT_ADDR ((uint32_t*)(REG_BASE + 0x680)) 7.276 +/* geometry command ports */ 7.277 +#define REG_MTX_MODE REG32(0x440) /* 1 */ 7.278 +#define REG_MTX_PUSH REG32(0x444) /* 0 */ 7.279 +#define REG_MTX_POP REG32(0x448) /* 1 */ 7.280 +#define REG_MTX_STORE REG32(0x44c) /* 1 */ 7.281 +#define REG_MTX_RESTORE REG32(0x450) /* 1 */ 7.282 +#define REG_MTX_IDENTITY REG32(0x454) /* 0 */ 7.283 +#define REG_MTX_LOAD_4X4 REG32(0x458) /* 16 */ 7.284 +#define REG_MTX_LOAD_4X3 REG32(0x45c) /* 12 */ 7.285 +#define REG_MTX_MULT_4X4 REG32(0x460) /* 16 */ 7.286 +#define REG_MTX_MULT_4X3 REG32(0x464) /* 12 */ 7.287 +#define REG_MTX_MULT_3X3 REG32(0x468) /* 9 */ 7.288 +#define REG_MTX_SCALE REG32(0x46c) /* 3 */ 7.289 +#define REG_MTX_TRANS REG32(0x470) /* 3 */ 7.290 +#define REG_COLOR REG32(0x480) /* 1 */ 7.291 +#define REG_NORMAL REG32(0x484) /* 1 */ 7.292 +#define REG_TEXCOORD REG32(0x488) /* 1 */ 7.293 +#define REG_VTX_16 REG32(0x48c) /* 2 */ 7.294 +#define REG_VTX_10 REG32(0x490) /* 1 */ 7.295 +#define REG_VTX_XY REG32(0x494) /* 1 */ 7.296 +#define REG_VTX_XZ REG32(0x498) /* 1 */ 7.297 +#define REG_VTX_YZ REG32(0x49c) /* 1 */ 7.298 +#define REG_VTX_DIFF REG32(0x4a0) /* 1 */ 7.299 +#define REG_POLYGON_ATTR REG32(0x4a4) /* 1 */ 7.300 +#define REG_TEXIMAGE_PARAM REG32(0x4a8) /* 1 */ 7.301 +#define REG_PLTT_BASE REG32(0x4ac) /* 1 */ 7.302 +#define REG_DIF_AMB REG32(0x4c0) /* 1 */ 7.303 +#define REG_SPE_EMI REG32(0x4c4) /* 1 */ 7.304 +#define REG_LIGHT_VECTOR REG32(0x4c8) /* 1 */ 7.305 +#define REG_LIGHT_COLOR REG32(0x4cc) /* 1 */ 7.306 +#define REG_SHININESS REG32(0x4d0) /* 32 */ 7.307 +#define REG_BEGIN_VTXS REG32(0x500) /* 1 */ 7.308 +#define REG_END_VTXS REG32(0x504) /* 0 */ 7.309 +#define REG_SWAP_BUFFERS REG32(0x540) /* 1 */ 7.310 +#define REG_VIEWPORT REG32(0x580) /* 1 */ 7.311 +#define REG_BOX_TEST REG32(0x5c0) /* 3 */ 7.312 +#define REG_POS_TEST REG32(0x5c4) /* 2 */ 7.313 +#define REG_VEC_TEST REG32(0x5c8) /* 1 */ 7.314 + 7.315 +/* geometry commands */ 7.316 +#define GCMD_MTX_MODE 0x10 /* 1 */ 7.317 +#define GCMD_MTX_PUSH 0x11 /* 0 */ 7.318 +#define GCMD_MTX_POP 0x12 /* 1 */ 7.319 +#define GCMD_MTX_STORE 0x13 /* 1 */ 7.320 +#define GCMD_MTX_RESTORE 0x14 /* 1 */ 7.321 +#define GCMD_MTX_IDENTITY 0x15 /* 0 */ 7.322 +#define GCMD_MTX_LOAD_4X4 0x16 /* 16 */ 7.323 +#define GCMD_MTX_LOAD_4X3 0x17 /* 12 */ 7.324 +#define GCMD_MTX_MULT_4X4 0x18 /* 16 */ 7.325 +#define GCMD_MTX_MULT_4X3 0x19 /* 12 */ 7.326 +#define GCMD_MTX_MULT_3X3 0x1a /* 9 */ 7.327 +#define GCMD_MTX_SCALE 0x1b /* 3 */ 7.328 +#define GCMD_MTX_TRANS 0x1c /* 3 */ 7.329 +#define GCMD_COLOR 0x20 /* 1 */ 7.330 +#define GCMD_NORMAL 0x21 /* 1 */ 7.331 +#define GCMD_TEXCOORD 0x22 /* 1 */ 7.332 +#define GCMD_VTX_16 0x23 /* 2 */ 7.333 +#define GCMD_VTX_10 0x24 /* 1 */ 7.334 +#define GCMD_VTX_XY 0x25 /* 1 */ 7.335 +#define GCMD_VTX_XZ 0x26 /* 1 */ 7.336 +#define GCMD_VTX_YZ 0x27 /* 1 */ 7.337 +#define GCMD_VTX_DIFF 0x28 /* 1 */ 7.338 +#define GCMD_POLYGON_ATTR 0x29 /* 1 */ 7.339 +#define GCMD_TEXIMAGE_PARAM 0x2a /* 1 */ 7.340 +#define GCMD_PLTT_BASE 0x2b /* 1 */ 7.341 +#define GCMD_DIF_AMB 0x30 /* 1 */ 7.342 +#define GCMD_SPE_EMI 0x31 /* 1 */ 7.343 +#define GCMD_LIGHT_VECTOR 0x32 /* 1 */ 7.344 +#define GCMD_LIGHT_COLOR 0x33 /* 1 */ 7.345 +#define GCMD_SHININESS 0x34 /* 32 */ 7.346 +#define GCMD_BEGIN_VTXS 0x40 /* 1 */ 7.347 +#define GCMD_END_VTXS 0x41 /* 0 */ 7.348 +#define GCMD_SWAP_BUFFERS 0x50 /* 1 */ 7.349 +#define GCMD_VIEWPORT 0x60 /* 1 */ 7.350 +#define GCMD_BOX_TEST 0x70 /* 3 */ 7.351 +#define GCMD_POS_TEST 0x71 /* 2 */ 7.352 +#define GCMD_VEC_TEST 0x72 /* 1 */ 7.353 + 7.354 +/* addresses of interest */ 7.355 +#define SHARED_WRAM_PTR ((void*)0x3000000) 7.356 +#define VRAM_BGA_PTR ((void*)0x6000000) 7.357 +#define VRAM_BGB_PTR ((void*)0x6200000) 7.358 +#define VRAM_OBJA_PTR ((void*)0x6400000) 7.359 +#define VRAM_OBJB_PTR ((void*)0x6600000) 7.360 +#define VRAM_LCDC_PTR ((void*)0x6800000) 7.361 +#define OAM_PTR ((void*)0x7000000) 7.362 + 7.363 +#endif /* DSREGS_H_ */
8.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 8.2 +++ b/src/main.c Sun Jan 28 20:05:26 2018 +0200 8.3 @@ -0,0 +1,121 @@ 8.4 +#include <stdint.h> 8.5 +#include <math.h> 8.6 +#include "dsregs.h" 8.7 +#include "ds3.h" 8.8 + 8.9 +static void xorpat(void *addr, int xsz, int ysz); 8.10 + 8.11 +static void *vram = VRAM_LCDC_PTR; 8.12 +static uint16_t *bgmem = VRAM_BGB_PTR; 8.13 + 8.14 +#define SIN_TAB_SZ 256 8.15 +static int32_t sintab[SIN_TAB_SZ]; 8.16 +static int32_t costab[SIN_TAB_SZ]; 8.17 + 8.18 +int main(void) 8.19 +{ 8.20 + int i; 8.21 + uint32_t frame; 8.22 + int32_t m[16] = { 8.23 + 0x10000, 0, 0, 0, 8.24 + 0, 0x10000, 0, 0, 8.25 + 0, 0, 0x10000, 0, 8.26 + 0, 0, 0, 0x10000 8.27 + }; 8.28 + 8.29 + REG_POWCNT1 = POWCNT1_LCD | POWCNT1_3DREND | POWCNT1_3DGEOM | POWCNT1_2DA | POWCNT1_2DB | POWCNT1_DSWAP; 8.30 + 8.31 + REG_DISPCNT = DISPCNT_MODE(1) | DISPCNT_BG0 | DISPCNT_BG0_3D; 8.32 + REG_B_DISPCNT = DISPCNT_MODE(1) | DISPCNT_BG2 | 5; 8.33 + 8.34 + REG_B_BG2CNT = BGXCNT_BM_256X256 | BGXCNT_BM16 | BGXCNT_OVF_WRAP; 8.35 + REG_B_BG2PA = 0x100; 8.36 + REG_B_BG2PB = 0; 8.37 + REG_B_BG2PC = 0; 8.38 + REG_B_BG2PD = 0x100; 8.39 + 8.40 + REG_VRAMCNT_A = VRAM_ENABLE; 8.41 + REG_VRAMCNT_C = VRAM_ENABLE | 4; 8.42 + 8.43 + xorpat(bgmem, 256, 256); 8.44 + 8.45 + for(i=0; i<SIN_TAB_SZ; i++) { 8.46 + float theta = (float)i * M_PI * 2.0 / (float)SIN_TAB_SZ; 8.47 + float s = sin(theta); 8.48 + float c = cos(theta); 8.49 + sintab[i] = (int32_t)(s * 65536.0); 8.50 + costab[i] = (int32_t)(c * 65536.0); 8.51 + } 8.52 + 8.53 + ds3_clear_color(RGB15(4, 4, 4), 31); 8.54 + ds3_clear_depth(0x7fff); 8.55 + ds3_viewport(0, 0, 256, 192); 8.56 + 8.57 + ds3_enable(DS3_ANTIALIAS); 8.58 + 8.59 + REG_POLYGON_ATTR = 0x001f00c0; /* alpha = 31, cull none */ 8.60 + 8.61 + ds3_matrix_mode(DS3_PROJECTION); 8.62 + ds3_load_identity(); 8.63 + ds3_scale(49152, 65536, 65536); 8.64 + 8.65 + for(;;) { 8.66 + int idx = frame & 0xff; 8.67 + int32_t scale = (sintab[(frame >> 1) & 0xff] >> 9) + 204; 8.68 + int32_t sa = ((sintab[idx] >> 8) * scale) >> 8; 8.69 + int32_t ca = ((costab[idx] >> 8) * scale) >> 8; 8.70 + /*float scale = 0.5 * sin(t * 0.8) + 0.8; 8.71 + int32_t sa = (int16_t)(sin(t) * 256 * scale); 8.72 + int32_t ca = (int16_t)(cos(t) * 256 * scale); 8.73 + */ 8.74 + 8.75 + int32_t x = ca * -128 + sa * -96 + (128 << 8); 8.76 + int32_t y = -sa * -128 + ca * -96 + (96 << 8); 8.77 + 8.78 + m[0] = ca << 8; m[1] = sa << 8; 8.79 + m[4] = -sa << 8; m[5] = ca << 8; 8.80 + 8.81 + ds3_matrix_mode(DS3_MODELVIEW); 8.82 + ds3_load_matrix(m); 8.83 + 8.84 + ds3_begin(DS3_QUADS); 8.85 + ds3_color(RGB15(31, 0, 0)); 8.86 + ds3_vertex3(-0x8000, -0x8000, 0); 8.87 + ds3_color(RGB15(0, 31, 0)); 8.88 + ds3_vertex3(0x8000, -0x8000, 0); 8.89 + ds3_color(RGB15(0, 0, 31)); 8.90 + ds3_vertex3(0x8000, 0x8000, 0); 8.91 + ds3_color(RGB15(31, 0, 31)); 8.92 + ds3_vertex3(-0x8000, 0x8000, 0); 8.93 + ds3_end(); 8.94 + 8.95 + ds3_swap_buffers(); 8.96 + while(REG_VCOUNT < 192); 8.97 + 8.98 + REG_B_BG2PA = ca; 8.99 + REG_B_BG2PB = sa; 8.100 + REG_B_BG2PC = -sa; 8.101 + REG_B_BG2PD = ca; 8.102 + REG_B_BG2X = x; 8.103 + REG_B_BG2Y = y; 8.104 + 8.105 + ++frame; 8.106 + } 8.107 + return 0; 8.108 +} 8.109 + 8.110 +static void xorpat(void *addr, int xsz, int ysz) 8.111 +{ 8.112 + int i, j; 8.113 + uint16_t *p = addr; 8.114 + 8.115 + for(i=0; i<ysz; i++) { 8.116 + for(j=0; j<xsz; j++) { 8.117 + int xor = i^j; 8.118 + uint16_t red = xor >> 2; 8.119 + uint16_t green = xor >> 1; 8.120 + uint16_t blue = xor; 8.121 + *p++ = 0x8000 | red | ((green & 0x1f) << 5) | ((blue & 0x1f) << 10); 8.122 + } 8.123 + } 8.124 +}
9.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 9.2 +++ b/src/startup/arm7entry.s Sun Jan 28 20:05:26 2018 +0200 9.3 @@ -0,0 +1,175 @@ 9.4 +@ vi:set filetype=armasm: 9.5 + .section ".crt0","ax" 9.6 + .global _start 9.7 + .align 4 9.8 + .arm 9.9 +_start: 9.10 + mov r0, #0x04000000 @ IME = 0; 9.11 + mov r1, #0 9.12 + str r1, [r0, #0x208] 9.13 + 9.14 + mov r0, #0x12 @ Switch to IRQ Mode 9.15 + msr cpsr, r0 9.16 + ldr sp, =__sp_irq @ Set IRQ stack 9.17 + 9.18 + mov r0, #0x13 @ Switch to SVC Mode 9.19 + msr cpsr, r0 9.20 + ldr sp, =__sp_svc @ Set SVC stack 9.21 + 9.22 + mov r0, #0x1F @ Switch to System Mode 9.23 + msr cpsr, r0 9.24 + ldr sp, =__sp_usr @ Set user stack 9.25 + 9.26 +#ifndef VRAM 9.27 + adr r1, __sync_start @ Perform ARM7<->ARM9 sync code 9.28 + ldr r2, =__arm7_start__ 9.29 + mov r3, #(__sync_end-__sync_start) 9.30 + mov r8, r2 9.31 + bl CopyMem 9.32 + mov r3, r8 9.33 + bl _blx_r3_stub 9.34 + 9.35 +@ Copy arm7 binary from LMA to VMA (EWRAM to IWRAM) 9.36 + adr r0, arm7lma @ Calculate ARM7 LMA 9.37 + ldr r1, [r0] 9.38 + add r1, r1, r0 9.39 + ldr r2, =__arm7_start__ 9.40 + ldr r4, =__arm7_end__ 9.41 + bl CopyMemCheck 9.42 + 9.43 +#else 9.44 + bl __sync_start 9.45 +#endif 9.46 + 9.47 + ldr r0, =__bss_start__ @ Clear BSS section to 0x00 9.48 + ldr r1, =__bss_end__ 9.49 + sub r1, r1, r0 9.50 + bl ClearMem 9.51 + 9.52 +#ifndef VRAM 9.53 + cmp r10, #1 9.54 + bne NotTWL 9.55 + ldr r1, =__dsimode @ set DSi mode flag 9.56 + strb r10, [r1] 9.57 + 9.58 + ldr r1, =0x02ffe1d8 @ Get ARM7i LMA from header 9.59 + ldr r1, [r1] 9.60 + ldr r2, =__arm7i_start__ 9.61 + ldr r4, =__arm7i_end__ 9.62 + bl CopyMemCheck 9.63 + 9.64 + ldr r0, =__twl_bss_start__ @ Clear TWL BSS section to 0x00 9.65 + ldr r1, =__twl_bss_end__ 9.66 + sub r1, r1, r0 9.67 + bl ClearMem 9.68 +#endif 9.69 + 9.70 +NotTWL: 9.71 + mov r0, #0 @ int argc 9.72 + mov r1, #0 @ char *argv[] 9.73 + ldr r3, =main 9.74 + mov r12, #0x4000000 @ tell arm9 we are ready 9.75 + mov r9, #0 9.76 + str r9, [r12, #0x180] 9.77 +_blx_r3_stub: 9.78 + bx r3 9.79 +infloop: 9.80 + b infloop 9.81 + 9.82 +#ifndef VRAM 9.83 +arm7lma: 9.84 + .word __arm7_lma__ - . 9.85 +#endif 9.86 + .pool 9.87 + 9.88 +@--------------------------------------------------------------------------------- 9.89 +@ ARM7<->ARM9 synchronization code 9.90 +@--------------------------------------------------------------------------------- 9.91 + 9.92 +__sync_start: 9.93 + push {lr} 9.94 + mov r12, #0x4000000 9.95 + mov r9, #0x0 9.96 + bl IPCSync 9.97 + mov r9, #(0x9<<8) 9.98 + str r9, [r12, #0x180] 9.99 + mov r9, #0xA 9.100 + bl IPCSync 9.101 + mov r9, #(0xB<<8) 9.102 + str r9, [r12, #0x180] 9.103 + mov r9, #0xC 9.104 + bl IPCSync 9.105 + mov r9, #(0xD<<8) 9.106 + str r9, [r12, #0x180] 9.107 +IPCRecvFlag: 9.108 + ldr r10, [r12, #0x180] 9.109 + and r10, r10, #0xF 9.110 + cmp r10, #0xC 9.111 + beq IPCRecvFlag 9.112 + pop {pc} 9.113 +IPCSync: 9.114 + ldr r10, [r12, #0x180] 9.115 + and r10, r10, #0xF 9.116 + cmp r10, r9 9.117 + bne IPCSync 9.118 + bx lr 9.119 +__sync_end: 9.120 + 9.121 +@--------------------------------------------------------------------------------- 9.122 +@ Clear memory to 0x00 if length != 0 9.123 +@ r0 = Start Address 9.124 +@ r1 = Length 9.125 +@--------------------------------------------------------------------------------- 9.126 +ClearMem: 9.127 +@--------------------------------------------------------------------------------- 9.128 + mov r2, #3 @ Round down to nearest word boundary 9.129 + add r1, r1, r2 @ Shouldn't be needed 9.130 + bics r1, r1, r2 @ Clear 2 LSB (and set Z) 9.131 + bxeq lr @ Quit if copy size is 0 9.132 + 9.133 + mov r2, #0 9.134 +ClrLoop: 9.135 + stmia r0!, {r2} 9.136 + subs r1, r1, #4 9.137 + bne ClrLoop 9.138 + bx lr 9.139 + 9.140 +@--------------------------------------------------------------------------------- 9.141 +@ Copy memory if length != 0 9.142 +@ r1 = Source Address 9.143 +@ r2 = Dest Address 9.144 +@ r4 = Dest Address + Length 9.145 +@--------------------------------------------------------------------------------- 9.146 +CopyMemCheck: 9.147 +@--------------------------------------------------------------------------------- 9.148 + cmp r1, r2 9.149 + bxeq lr 9.150 + 9.151 + sub r3, r4, r2 @ Is there any data to copy? 9.152 +@--------------------------------------------------------------------------------- 9.153 +@ Copy memory 9.154 +@ r1 = Source Address 9.155 +@ r2 = Dest Address 9.156 +@ r3 = Length 9.157 +@--------------------------------------------------------------------------------- 9.158 +CopyMem: 9.159 +@--------------------------------------------------------------------------------- 9.160 + mov r0, #3 @ These commands are used in cases where 9.161 + add r3, r3, r0 @ the length is not a multiple of 4, 9.162 + bics r3, r3, r0 @ even though it should be. 9.163 + bxeq lr @ Length is zero, so exit 9.164 +CIDLoop: 9.165 + ldmia r1!, {r0} 9.166 + stmia r2!, {r0} 9.167 + subs r3, r3, #4 9.168 + bne CIDLoop 9.169 + bx lr 9.170 + 9.171 +@--------------------------------------------------------------------------------- 9.172 + .align 9.173 + .pool 9.174 + 9.175 + .global __dsimode 9.176 +__dsimode: .word 9.177 + .end 9.178 +@---------------------------------------------------------------------------------
10.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 10.2 +++ b/src/startup/arm9entry.s Sun Jan 28 20:05:26 2018 +0200 10.3 @@ -0,0 +1,192 @@ 10.4 +@ vi:set filetype=armasm: 10.5 + .arch armv5te 10.6 + .cpu arm946e-s 10.7 + .section ".crt0","ax" 10.8 + .global _start 10.9 + .align 4 10.10 + .arm 10.11 +_start: 10.12 + mov r0, #0x04000000 @ IME = 0; 10.13 + str r0, [r0, #0x208] 10.14 + 10.15 + @ set sensible stacks to allow bios call 10.16 + 10.17 + mov r0, #0x13 @ Switch to SVC Mode 10.18 + msr cpsr, r0 10.19 + mov r1,#0x03000000 10.20 + sub r1,r1,#0x1000 10.21 + mov sp,r1 10.22 + mov r0, #0x1F @ Switch to System Mode 10.23 + msr cpsr, r0 10.24 + sub r1,r1,#0x100 10.25 + mov sp,r1 10.26 + 10.27 + ldr r3, =mpu_setup 10.28 + blx r3 10.29 + 10.30 + mov r0, #0x12 @ Switch to IRQ Mode 10.31 + msr cpsr, r0 10.32 + ldr sp, =__sp_irq @ Set IRQ stack 10.33 + 10.34 + mov r0, #0x13 @ Switch to SVC Mode 10.35 + msr cpsr, r0 10.36 + ldr sp, =__sp_svc @ Set SVC stack 10.37 + 10.38 + mov r0, #0x1F @ Switch to System Mode 10.39 + msr cpsr, r0 10.40 + ldr sp, =__sp_usr @ Set user stack 10.41 + 10.42 + mov r12, #0x4000000 @ Read system ROM status (NTR/TWL) 10.43 + ldrb r11, [r12,r12,lsr #12] 10.44 + and r11, r11, #0x3 10.45 + 10.46 + b skip_sync 10.47 + 10.48 + mov r9, #(0x0<<8) @ Synchronize with ARM7 10.49 + str r9, [r12, #0x180] 10.50 + mov r9, #0x9 10.51 + bl IPCSync 10.52 + mov r9, #(0xA<<8) 10.53 + str r9, [r12, #0x180] 10.54 + mov r9, #0xB 10.55 + bl IPCSync 10.56 + mov r9, #(0xC<<8) 10.57 + str r9, [r12, #0x180] 10.58 + mov r9, #0xD 10.59 + bl IPCSync 10.60 + mov r9, r11, lsl #8 10.61 + str r9, [r12, #0x180] 10.62 + mov r9, #0 10.63 + bl IPCSync 10.64 + str r9, [r12, #0x180] 10.65 + 10.66 +skip_sync: 10.67 + 10.68 + ldr r1, =__itcm_lma @ Copy instruction tightly coupled memory (itcm section) from LMA to VMA 10.69 + ldr r2, =__itcm_start 10.70 + ldr r4, =__itcm_end 10.71 + bl CopyMemCheck 10.72 + 10.73 + ldr r1, =__vectors_lma @ Copy reserved vectors area (itcm section) from LMA to VMA 10.74 + ldr r2, =__vectors_start 10.75 + ldr r4, =__vectors_end 10.76 + bl CopyMemCheck 10.77 + 10.78 + ldr r1, =__dtcm_lma @ Copy data tightly coupled memory (dtcm section) from LMA to VMA 10.79 + ldr r2, =__dtcm_start 10.80 + ldr r4, =__dtcm_end 10.81 + bl CopyMemCheck 10.82 + 10.83 + cmp r11, #1 10.84 + ldrne r10, =__end__ @ (DS mode) heap start 10.85 + ldreq r10, =__twl_end__ @ (DSi mode) heap start 10.86 + 10.87 + ldr r0, =__bss_start__ @ Clear BSS section 10.88 + ldr r1, =__bss_end__ 10.89 + sub r1, r1, r0 10.90 + bl ClearMem 10.91 + 10.92 + ldr r0, =__sbss_start @ Clear SBSS section 10.93 + ldr r1, =__sbss_end 10.94 + sub r1, r1, r0 10.95 + bl ClearMem 10.96 + 10.97 + cmp r11, #1 10.98 + bne NotTWL 10.99 + ldr r9, =__dsimode @ set DSi mode flag 10.100 + strb r11, [r9] 10.101 + 10.102 + @ Copy TWL area (arm9i section) from LMA to VMA 10.103 + ldr r1, =0x02ffe1c8 @ Get ARM9i LMA from header 10.104 + ldr r1, [r1] 10.105 + 10.106 + ldr r2, =__arm9i_start__ 10.107 + cmp r1, r2 @ skip copy if LMA=VMA 10.108 + ldrne r4, =__arm9i_end__ 10.109 + blne CopyMemCheck 10.110 + 10.111 + ldr r0, =__twl_bss_start__ @ Clear TWL BSS section 10.112 + ldr r1, =__twl_bss_end__ 10.113 + sub r1, r1, r0 10.114 + bl ClearMem 10.115 + 10.116 +NotTWL: 10.117 + ldr r0, =__secure_area__ 10.118 + ldr r3, =main 10.119 + bx r3 @ jump to user code 10.120 +infloop: 10.121 + b infloop 10.122 + 10.123 + 10.124 + 10.125 +@--------------------------------------------------------------------------------- 10.126 +@ Clear memory to 0x00 if length != 0 10.127 +@ r0 = Start Address 10.128 +@ r1 = Length 10.129 +@--------------------------------------------------------------------------------- 10.130 +ClearMem: 10.131 +@--------------------------------------------------------------------------------- 10.132 + mov r2, #3 @ Round down to nearest word boundary 10.133 + add r1, r1, r2 @ Shouldn't be needed 10.134 + bics r1, r1, r2 @ Clear 2 LSB (and set Z) 10.135 + bxeq lr @ Quit if copy size is 0 10.136 + 10.137 + mov r2, #0 10.138 +ClrLoop: 10.139 + stmia r0!, {r2} 10.140 + subs r1, r1, #4 10.141 + bne ClrLoop 10.142 + 10.143 + bx lr 10.144 + 10.145 +@--------------------------------------------------------------------------------- 10.146 +@ Copy memory if length != 0 10.147 +@ r1 = Source Address 10.148 +@ r2 = Dest Address 10.149 +@ r4 = Dest Address + Length 10.150 +@--------------------------------------------------------------------------------- 10.151 +CopyMemCheck: 10.152 +@--------------------------------------------------------------------------------- 10.153 + sub r3, r4, r2 @ Is there any data to copy? 10.154 +@--------------------------------------------------------------------------------- 10.155 +@ Copy memory 10.156 +@ r1 = Source Address 10.157 +@ r2 = Dest Address 10.158 +@ r3 = Length 10.159 +@--------------------------------------------------------------------------------- 10.160 +CopyMem: 10.161 +@--------------------------------------------------------------------------------- 10.162 + mov r0, #3 @ These commands are used in cases where 10.163 + add r3, r3, r0 @ the length is not a multiple of 4, 10.164 + bics r3, r3, r0 @ even though it should be. 10.165 + bxeq lr @ Length is zero, so exit 10.166 +CIDLoop: 10.167 + ldmia r1!, {r0} 10.168 + stmia r2!, {r0} 10.169 + subs r3, r3, #4 10.170 + bne CIDLoop 10.171 + 10.172 + bx lr 10.173 + 10.174 +@ Synchronize with ARM7 10.175 +IPCSync: 10.176 + ldr r10, [r12, #0x180] 10.177 + and r10, r10, #0xF 10.178 + cmp r10, r9 10.179 + bne IPCSync 10.180 + bx lr 10.181 + 10.182 + 10.183 + .align 10.184 + .pool 10.185 + 10.186 + .data 10.187 + .global __dsimode 10.188 +__dsimode: 10.189 + .word 0 10.190 + 10.191 + .section ".secure","a" 10.192 + .align 2 10.193 + .global __secure_area__ 10.194 +__secure_area__: 10.195 + .space 2048, 0
11.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 11.2 +++ b/src/startup/mpu_setup.S Sun Jan 28 20:05:26 2018 +0200 11.3 @@ -0,0 +1,203 @@ 11.4 +@ vi:set filetype=armasm: 11.5 +#define PAGE_4K (0b01011 << 1) 11.6 +#define PAGE_8K (0b01100 << 1) 11.7 +#define PAGE_16K (0b01101 << 1) 11.8 +#define PAGE_32K (0b01110 << 1) 11.9 +#define PAGE_64K (0b01111 << 1) 11.10 +#define PAGE_128K (0b10000 << 1) 11.11 +#define PAGE_256K (0b10001 << 1) 11.12 +#define PAGE_512K (0b10010 << 1) 11.13 +#define PAGE_1M (0b10011 << 1) 11.14 +#define PAGE_2M (0b10100 << 1) 11.15 +#define PAGE_4M (0b10101 << 1) 11.16 +#define PAGE_8M (0b10110 << 1) 11.17 +#define PAGE_16M (0b10111 << 1) 11.18 +#define PAGE_32M (0b11000 << 1) 11.19 +#define PAGE_64M (0b11001 << 1) 11.20 +#define PAGE_128M (0b11010 << 1) 11.21 +#define PAGE_256M (0b11011 << 1) 11.22 +#define PAGE_512M (0b11100 << 1) 11.23 +#define PAGE_1G (0b11101 << 1) 11.24 +#define PAGE_2G (0b11110 << 1) 11.25 +#define PAGE_4G (0b11111 << 1) 11.26 + 11.27 +#define ITCM_LOAD (1<<19) 11.28 +#define ITCM_ENABLE (1<<18) 11.29 +#define DTCM_LOAD (1<<17) 11.30 +#define DTCM_ENABLE (1<<16) 11.31 +#define DISABLE_TBIT (1<<15) 11.32 +#define ROUND_ROBIN (1<<14) 11.33 +#define ALT_VECTORS (1<<13) 11.34 +#define ICACHE_ENABLE (1<<12) 11.35 +#define BIG_ENDIAN (1<<7) 11.36 +#define DCACHE_ENABLE (1<<2) 11.37 +#define PROTECT_ENABLE (1<<0) 11.38 + 11.39 + .arch armv5te 11.40 + .cpu arm946e-s 11.41 + 11.42 + .text 11.43 + .arm 11.44 + 11.45 + .global mpu_setup 11.46 + .align 2 11.47 +mpu_setup: 11.48 +@ turn the power on for M3 11.49 + ldr r1, =0x8203 11.50 + mov r0, #0x04000000 11.51 + add r0, r0, #0x304 11.52 + strh r1, [r0] 11.53 + 11.54 + ldr r1, =0x00002078 @ disable TCM and protection unit 11.55 + mcr p15, 0, r1, c1, c0 11.56 + 11.57 +@ Protection Unit Setup added by Sasq 11.58 + @ Disable cache 11.59 + mov r0, #0 11.60 + mcr p15, 0, r0, c7, c5, 0 @ Instruction cache 11.61 + mcr p15, 0, r0, c7, c6, 0 @ Data cache 11.62 + 11.63 + @ Wait for write buffer to empty 11.64 + mcr p15, 0, r0, c7, c10, 4 11.65 + 11.66 + ldr r0, =__dtcm_start 11.67 + orr r0,r0,#0x0a 11.68 + mcr p15, 0, r0, c9, c1,0 @ DTCM base = __dtcm_start, size = 16 KB 11.69 + 11.70 + mov r0,#0x20 11.71 + mcr p15, 0, r0, c9, c1,1 @ ITCM base = 0 , size = 32 MB 11.72 + 11.73 +@ Setup memory regions similar to Release Version 11.74 + @ Region 0 - IO registers 11.75 + ldr r0,=( PAGE_64M | 0x04000000 | 1) 11.76 + mcr p15, 0, r0, c6, c0, 0 11.77 + 11.78 + @ Region 1 - System ROM 11.79 + ldr r0,=( PAGE_64K | 0xFFFF0000 | 1) 11.80 + mcr p15, 0, r0, c6, c1, 0 11.81 + 11.82 + @ Region 2 - alternate vector base 11.83 + ldr r0,=( PAGE_4K | 0x00000000 | 1) 11.84 + mcr p15, 0, r0, c6, c2, 0 11.85 + 11.86 + @ Region 5 - DTCM 11.87 + ldr r0,=__dtcm_start 11.88 + orr r0,r0,#(PAGE_16K | 1) 11.89 + mcr p15, 0, r0, c6, c5, 0 11.90 + 11.91 + @ Region 4 - ITCM 11.92 + ldr r0,=__itcm_start 11.93 + 11.94 + @ align to 32k boundary 11.95 + mov r0,r0,lsr #15 11.96 + mov r0,r0,lsl #15 11.97 + 11.98 + orr r0,r0,#(PAGE_32K | 1) 11.99 + mcr p15, 0, r0, c6, c4, 0 11.100 + 11.101 + ldr r0,=0x4004008 11.102 + ldr r0,[r0] 11.103 + tst r0,#0x8000 11.104 + bne dsi_mode 11.105 + 11.106 + swi 0xf0000 11.107 + 11.108 + ldr r1,=( PAGE_128M | 0x08000000 | 1) 11.109 + cmp r0,#0 11.110 + bne debug_mode 11.111 + 11.112 + ldr r3,=( PAGE_4M | 0x02000000 | 1) 11.113 + ldr r2,=( PAGE_16M | 0x02000000 | 1) 11.114 + mov r8,#0x02400000 11.115 + 11.116 + ldr r9,=dsmasks 11.117 + b setregions 11.118 + 11.119 +debug_mode: 11.120 + ldr r3,=( PAGE_8M | 0x02000000 | 1) 11.121 + ldr r2,=( PAGE_8M | 0x02800000 | 1) 11.122 + mov r8,#0x02800000 11.123 + ldr r9,=debugmasks 11.124 + b setregions 11.125 + 11.126 +dsi_mode: 11.127 + tst r0,#0x4000 11.128 + ldr r1,=( PAGE_8M | 0x03000000 | 1) 11.129 + ldr r3,=( PAGE_16M | 0x02000000 | 1) 11.130 + ldreq r2,=( PAGE_16M | 0x0C000000 | 1) 11.131 + ldrne r2,=( PAGE_32M | 0x0C000000 | 1) @ DSi debugger extended iwram 11.132 + mov r8,#0x03000000 11.133 + ldr r9,=dsimasks 11.134 + 11.135 +setregions: 11.136 + @ Region 3 - DS Accessory (GBA Cart) / DSi switchable iwram 11.137 + mcr p15, 0, r1, c6, c3, 0 11.138 + 11.139 + @ Region 6 - non cacheable main ram 11.140 + mcr p15, 0, r2, c6, c6, 0 11.141 + 11.142 + @ Region 7 - cacheable main ram 11.143 + mcr p15, 0, r3, c6, c7, 0 11.144 + 11.145 + 11.146 + @ Write buffer enable 11.147 + ldr r0,=0b10000000 11.148 + mcr p15, 0, r0, c3, c0, 0 11.149 + 11.150 + @ DCache & ICache enable 11.151 + ldr r0,=0b10000010 11.152 + mcr p15, 0, r0, c2, c0, 0 11.153 + mcr p15, 0, r0, c2, c0, 1 11.154 + 11.155 + @ IAccess 11.156 + ldr r0,=0x33333363 11.157 + mcr p15, 0, r0, c5, c0, 3 11.158 + 11.159 + @ DAccess 11.160 + mcr p15, 0, r0, c5, c0, 2 11.161 + 11.162 + @ Enable ICache, DCache, ITCM & DTCM 11.163 + mrc p15, 0, r0, c1, c0, 0 11.164 + ldr r1,= ITCM_ENABLE | DTCM_ENABLE | ICACHE_ENABLE | DCACHE_ENABLE | PROTECT_ENABLE 11.165 + orr r0,r0,r1 11.166 + mcr p15, 0, r0, c1, c0, 0 11.167 + 11.168 + ldr r0,=masks 11.169 + str r9,[r0] 11.170 + 11.171 + bx lr 11.172 + 11.173 + .global memCached 11.174 + .align 2 11.175 +memCached: 11.176 + ldr r1,=masks 11.177 + ldr r1, [r1] 11.178 + ldr r2,[r1],#4 11.179 + and r0,r0,r2 11.180 + ldr r2,[r1] 11.181 + orr r0,r0,r2 11.182 + bx lr 11.183 + 11.184 + .global memUncached 11.185 + .align 2 11.186 +memUncached: 11.187 + ldr r1,=masks 11.188 + ldr r1, [r1] 11.189 + ldr r2,[r1],#8 11.190 + and r0,r0,r2 11.191 + ldr r2,[r1] 11.192 + orr r0,r0,r2 11.193 + bx lr 11.194 + 11.195 + .data 11.196 + .align 2 11.197 + 11.198 +dsmasks: 11.199 + .word 0x003fffff, 0x02000000, 0x02c00000 11.200 +debugmasks: 11.201 + .word 0x007fffff, 0x02000000, 0x02800000 11.202 +dsimasks: 11.203 + .word 0x00ffffff, 0x02000000, 0x0c000000 11.204 + 11.205 +masks: .word dsmasks 11.206 +