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1 @ vi:set filetype=armasm:
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2 #define PAGE_4K (0b01011 << 1)
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3 #define PAGE_8K (0b01100 << 1)
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4 #define PAGE_16K (0b01101 << 1)
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5 #define PAGE_32K (0b01110 << 1)
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6 #define PAGE_64K (0b01111 << 1)
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7 #define PAGE_128K (0b10000 << 1)
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8 #define PAGE_256K (0b10001 << 1)
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9 #define PAGE_512K (0b10010 << 1)
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10 #define PAGE_1M (0b10011 << 1)
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11 #define PAGE_2M (0b10100 << 1)
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12 #define PAGE_4M (0b10101 << 1)
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13 #define PAGE_8M (0b10110 << 1)
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14 #define PAGE_16M (0b10111 << 1)
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15 #define PAGE_32M (0b11000 << 1)
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16 #define PAGE_64M (0b11001 << 1)
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17 #define PAGE_128M (0b11010 << 1)
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18 #define PAGE_256M (0b11011 << 1)
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19 #define PAGE_512M (0b11100 << 1)
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20 #define PAGE_1G (0b11101 << 1)
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21 #define PAGE_2G (0b11110 << 1)
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22 #define PAGE_4G (0b11111 << 1)
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23
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24 #define ITCM_LOAD (1<<19)
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25 #define ITCM_ENABLE (1<<18)
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26 #define DTCM_LOAD (1<<17)
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27 #define DTCM_ENABLE (1<<16)
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28 #define DISABLE_TBIT (1<<15)
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29 #define ROUND_ROBIN (1<<14)
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30 #define ALT_VECTORS (1<<13)
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31 #define ICACHE_ENABLE (1<<12)
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32 #define BIG_ENDIAN (1<<7)
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33 #define DCACHE_ENABLE (1<<2)
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34 #define PROTECT_ENABLE (1<<0)
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35
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36 .arch armv5te
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37 .cpu arm946e-s
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38
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39 .text
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40 .arm
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41
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42 .global mpu_setup
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43 .align 2
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44 mpu_setup:
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45 @ turn the power on for M3
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46 ldr r1, =0x8203
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47 mov r0, #0x04000000
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48 add r0, r0, #0x304
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49 strh r1, [r0]
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50
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51 ldr r1, =0x00002078 @ disable TCM and protection unit
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52 mcr p15, 0, r1, c1, c0
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53
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54 @ Protection Unit Setup added by Sasq
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55 @ Disable cache
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56 mov r0, #0
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57 mcr p15, 0, r0, c7, c5, 0 @ Instruction cache
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58 mcr p15, 0, r0, c7, c6, 0 @ Data cache
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59
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60 @ Wait for write buffer to empty
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61 mcr p15, 0, r0, c7, c10, 4
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62
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63 ldr r0, =__dtcm_start
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64 orr r0,r0,#0x0a
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65 mcr p15, 0, r0, c9, c1,0 @ DTCM base = __dtcm_start, size = 16 KB
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66
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67 mov r0,#0x20
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68 mcr p15, 0, r0, c9, c1,1 @ ITCM base = 0 , size = 32 MB
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69
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70 @ Setup memory regions similar to Release Version
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71 @ Region 0 - IO registers
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72 ldr r0,=( PAGE_64M | 0x04000000 | 1)
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73 mcr p15, 0, r0, c6, c0, 0
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74
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75 @ Region 1 - System ROM
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76 ldr r0,=( PAGE_64K | 0xFFFF0000 | 1)
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77 mcr p15, 0, r0, c6, c1, 0
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78
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79 @ Region 2 - alternate vector base
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80 ldr r0,=( PAGE_4K | 0x00000000 | 1)
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81 mcr p15, 0, r0, c6, c2, 0
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82
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83 @ Region 5 - DTCM
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84 ldr r0,=__dtcm_start
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85 orr r0,r0,#(PAGE_16K | 1)
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86 mcr p15, 0, r0, c6, c5, 0
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87
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88 @ Region 4 - ITCM
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89 ldr r0,=__itcm_start
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90
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91 @ align to 32k boundary
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92 mov r0,r0,lsr #15
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93 mov r0,r0,lsl #15
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94
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95 orr r0,r0,#(PAGE_32K | 1)
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96 mcr p15, 0, r0, c6, c4, 0
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97
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98 ldr r0,=0x4004008
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99 ldr r0,[r0]
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100 tst r0,#0x8000
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101 bne dsi_mode
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102
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103 swi 0xf0000
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104
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105 ldr r1,=( PAGE_128M | 0x08000000 | 1)
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106 cmp r0,#0
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107 bne debug_mode
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108
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109 ldr r3,=( PAGE_4M | 0x02000000 | 1)
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110 ldr r2,=( PAGE_16M | 0x02000000 | 1)
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111 mov r8,#0x02400000
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112
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113 ldr r9,=dsmasks
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114 b setregions
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115
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116 debug_mode:
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117 ldr r3,=( PAGE_8M | 0x02000000 | 1)
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118 ldr r2,=( PAGE_8M | 0x02800000 | 1)
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119 mov r8,#0x02800000
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120 ldr r9,=debugmasks
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121 b setregions
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122
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123 dsi_mode:
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124 tst r0,#0x4000
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125 ldr r1,=( PAGE_8M | 0x03000000 | 1)
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126 ldr r3,=( PAGE_16M | 0x02000000 | 1)
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127 ldreq r2,=( PAGE_16M | 0x0C000000 | 1)
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128 ldrne r2,=( PAGE_32M | 0x0C000000 | 1) @ DSi debugger extended iwram
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129 mov r8,#0x03000000
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130 ldr r9,=dsimasks
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131
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132 setregions:
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133 @ Region 3 - DS Accessory (GBA Cart) / DSi switchable iwram
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134 mcr p15, 0, r1, c6, c3, 0
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135
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136 @ Region 6 - non cacheable main ram
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137 mcr p15, 0, r2, c6, c6, 0
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138
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139 @ Region 7 - cacheable main ram
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140 mcr p15, 0, r3, c6, c7, 0
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141
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142
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143 @ Write buffer enable
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144 ldr r0,=0b10000000
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145 mcr p15, 0, r0, c3, c0, 0
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146
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147 @ DCache & ICache enable
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148 ldr r0,=0b10000010
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149 mcr p15, 0, r0, c2, c0, 0
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150 mcr p15, 0, r0, c2, c0, 1
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151
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152 @ IAccess
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153 ldr r0,=0x33333363
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154 mcr p15, 0, r0, c5, c0, 3
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155
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156 @ DAccess
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157 mcr p15, 0, r0, c5, c0, 2
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158
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159 @ Enable ICache, DCache, ITCM & DTCM
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160 mrc p15, 0, r0, c1, c0, 0
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161 ldr r1,= ITCM_ENABLE | DTCM_ENABLE | ICACHE_ENABLE | DCACHE_ENABLE | PROTECT_ENABLE
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162 orr r0,r0,r1
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163 mcr p15, 0, r0, c1, c0, 0
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164
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165 ldr r0,=masks
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166 str r9,[r0]
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167
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168 bx lr
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169
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170 .global memCached
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171 .align 2
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172 memCached:
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173 ldr r1,=masks
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174 ldr r1, [r1]
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175 ldr r2,[r1],#4
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176 and r0,r0,r2
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177 ldr r2,[r1]
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178 orr r0,r0,r2
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179 bx lr
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180
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181 .global memUncached
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182 .align 2
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183 memUncached:
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184 ldr r1,=masks
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185 ldr r1, [r1]
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186 ldr r2,[r1],#8
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187 and r0,r0,r2
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188 ldr r2,[r1]
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189 orr r0,r0,r2
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190 bx lr
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191
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192 .data
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193 .align 2
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194
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195 dsmasks:
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196 .word 0x003fffff, 0x02000000, 0x02c00000
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197 debugmasks:
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198 .word 0x007fffff, 0x02000000, 0x02800000
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199 dsimasks:
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200 .word 0x00ffffff, 0x02000000, 0x0c000000
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201
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202 masks: .word dsmasks
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203
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