nds_test2
view src/startup/mpu_setup.S @ 0:abcaf667f2bd
initial commit (3d + 2d)
| author | John Tsiombikas <nuclear@member.fsf.org> |
|---|---|
| date | Sun, 28 Jan 2018 20:05:26 +0200 |
| parents | |
| children |
line source
1 @ vi:set filetype=armasm:
2 #define PAGE_4K (0b01011 << 1)
3 #define PAGE_8K (0b01100 << 1)
4 #define PAGE_16K (0b01101 << 1)
5 #define PAGE_32K (0b01110 << 1)
6 #define PAGE_64K (0b01111 << 1)
7 #define PAGE_128K (0b10000 << 1)
8 #define PAGE_256K (0b10001 << 1)
9 #define PAGE_512K (0b10010 << 1)
10 #define PAGE_1M (0b10011 << 1)
11 #define PAGE_2M (0b10100 << 1)
12 #define PAGE_4M (0b10101 << 1)
13 #define PAGE_8M (0b10110 << 1)
14 #define PAGE_16M (0b10111 << 1)
15 #define PAGE_32M (0b11000 << 1)
16 #define PAGE_64M (0b11001 << 1)
17 #define PAGE_128M (0b11010 << 1)
18 #define PAGE_256M (0b11011 << 1)
19 #define PAGE_512M (0b11100 << 1)
20 #define PAGE_1G (0b11101 << 1)
21 #define PAGE_2G (0b11110 << 1)
22 #define PAGE_4G (0b11111 << 1)
24 #define ITCM_LOAD (1<<19)
25 #define ITCM_ENABLE (1<<18)
26 #define DTCM_LOAD (1<<17)
27 #define DTCM_ENABLE (1<<16)
28 #define DISABLE_TBIT (1<<15)
29 #define ROUND_ROBIN (1<<14)
30 #define ALT_VECTORS (1<<13)
31 #define ICACHE_ENABLE (1<<12)
32 #define BIG_ENDIAN (1<<7)
33 #define DCACHE_ENABLE (1<<2)
34 #define PROTECT_ENABLE (1<<0)
36 .arch armv5te
37 .cpu arm946e-s
39 .text
40 .arm
42 .global mpu_setup
43 .align 2
44 mpu_setup:
45 @ turn the power on for M3
46 ldr r1, =0x8203
47 mov r0, #0x04000000
48 add r0, r0, #0x304
49 strh r1, [r0]
51 ldr r1, =0x00002078 @ disable TCM and protection unit
52 mcr p15, 0, r1, c1, c0
54 @ Protection Unit Setup added by Sasq
55 @ Disable cache
56 mov r0, #0
57 mcr p15, 0, r0, c7, c5, 0 @ Instruction cache
58 mcr p15, 0, r0, c7, c6, 0 @ Data cache
60 @ Wait for write buffer to empty
61 mcr p15, 0, r0, c7, c10, 4
63 ldr r0, =__dtcm_start
64 orr r0,r0,#0x0a
65 mcr p15, 0, r0, c9, c1,0 @ DTCM base = __dtcm_start, size = 16 KB
67 mov r0,#0x20
68 mcr p15, 0, r0, c9, c1,1 @ ITCM base = 0 , size = 32 MB
70 @ Setup memory regions similar to Release Version
71 @ Region 0 - IO registers
72 ldr r0,=( PAGE_64M | 0x04000000 | 1)
73 mcr p15, 0, r0, c6, c0, 0
75 @ Region 1 - System ROM
76 ldr r0,=( PAGE_64K | 0xFFFF0000 | 1)
77 mcr p15, 0, r0, c6, c1, 0
79 @ Region 2 - alternate vector base
80 ldr r0,=( PAGE_4K | 0x00000000 | 1)
81 mcr p15, 0, r0, c6, c2, 0
83 @ Region 5 - DTCM
84 ldr r0,=__dtcm_start
85 orr r0,r0,#(PAGE_16K | 1)
86 mcr p15, 0, r0, c6, c5, 0
88 @ Region 4 - ITCM
89 ldr r0,=__itcm_start
91 @ align to 32k boundary
92 mov r0,r0,lsr #15
93 mov r0,r0,lsl #15
95 orr r0,r0,#(PAGE_32K | 1)
96 mcr p15, 0, r0, c6, c4, 0
98 ldr r0,=0x4004008
99 ldr r0,[r0]
100 tst r0,#0x8000
101 bne dsi_mode
103 swi 0xf0000
105 ldr r1,=( PAGE_128M | 0x08000000 | 1)
106 cmp r0,#0
107 bne debug_mode
109 ldr r3,=( PAGE_4M | 0x02000000 | 1)
110 ldr r2,=( PAGE_16M | 0x02000000 | 1)
111 mov r8,#0x02400000
113 ldr r9,=dsmasks
114 b setregions
116 debug_mode:
117 ldr r3,=( PAGE_8M | 0x02000000 | 1)
118 ldr r2,=( PAGE_8M | 0x02800000 | 1)
119 mov r8,#0x02800000
120 ldr r9,=debugmasks
121 b setregions
123 dsi_mode:
124 tst r0,#0x4000
125 ldr r1,=( PAGE_8M | 0x03000000 | 1)
126 ldr r3,=( PAGE_16M | 0x02000000 | 1)
127 ldreq r2,=( PAGE_16M | 0x0C000000 | 1)
128 ldrne r2,=( PAGE_32M | 0x0C000000 | 1) @ DSi debugger extended iwram
129 mov r8,#0x03000000
130 ldr r9,=dsimasks
132 setregions:
133 @ Region 3 - DS Accessory (GBA Cart) / DSi switchable iwram
134 mcr p15, 0, r1, c6, c3, 0
136 @ Region 6 - non cacheable main ram
137 mcr p15, 0, r2, c6, c6, 0
139 @ Region 7 - cacheable main ram
140 mcr p15, 0, r3, c6, c7, 0
143 @ Write buffer enable
144 ldr r0,=0b10000000
145 mcr p15, 0, r0, c3, c0, 0
147 @ DCache & ICache enable
148 ldr r0,=0b10000010
149 mcr p15, 0, r0, c2, c0, 0
150 mcr p15, 0, r0, c2, c0, 1
152 @ IAccess
153 ldr r0,=0x33333363
154 mcr p15, 0, r0, c5, c0, 3
156 @ DAccess
157 mcr p15, 0, r0, c5, c0, 2
159 @ Enable ICache, DCache, ITCM & DTCM
160 mrc p15, 0, r0, c1, c0, 0
161 ldr r1,= ITCM_ENABLE | DTCM_ENABLE | ICACHE_ENABLE | DCACHE_ENABLE | PROTECT_ENABLE
162 orr r0,r0,r1
163 mcr p15, 0, r0, c1, c0, 0
165 ldr r0,=masks
166 str r9,[r0]
168 bx lr
170 .global memCached
171 .align 2
172 memCached:
173 ldr r1,=masks
174 ldr r1, [r1]
175 ldr r2,[r1],#4
176 and r0,r0,r2
177 ldr r2,[r1]
178 orr r0,r0,r2
179 bx lr
181 .global memUncached
182 .align 2
183 memUncached:
184 ldr r1,=masks
185 ldr r1, [r1]
186 ldr r2,[r1],#8
187 and r0,r0,r2
188 ldr r2,[r1]
189 orr r0,r0,r2
190 bx lr
192 .data
193 .align 2
195 dsmasks:
196 .word 0x003fffff, 0x02000000, 0x02c00000
197 debugmasks:
198 .word 0x007fffff, 0x02000000, 0x02800000
199 dsimasks:
200 .word 0x00ffffff, 0x02000000, 0x0c000000
202 masks: .word dsmasks