| rev |
line source |
|
nuclear@4
|
1 #ifndef VDP_H_
|
|
nuclear@4
|
2 #define VDP_H_
|
|
nuclear@4
|
3
|
|
nuclear@4
|
4 #include <stdint.h>
|
|
nuclear@4
|
5
|
|
nuclear@4
|
6 #define VDP_PORT_DATA (*(volatile uint16_t*)0xc00000)
|
|
nuclear@4
|
7 #define VDP_PORT_DATA32 (*(volatile uint32_t*)0xc00000)
|
|
nuclear@4
|
8 #define VDP_PORT_CTL (*(volatile uint16_t*)0xc00004)
|
|
nuclear@4
|
9 #define VDP_PORT_CTL32 (*(volatile uint32_t*)0xc00004)
|
|
nuclear@4
|
10 #define VDP_PORT_HVCOUNT (*(volatile uint16_t*)0xc00008)
|
|
nuclear@4
|
11 #define VDP_PORT_PSG (*(volatile uint16_t*)0xc00010)
|
|
nuclear@4
|
12
|
|
nuclear@4
|
13 /* control register read flags */
|
|
nuclear@4
|
14 #define VDP_CTL_PAL_BIT 0x0001
|
|
nuclear@4
|
15 #define VDP_CTL_HBLANK_BIT 0x0002
|
|
nuclear@4
|
16 #define VDP_CTL_VBLANK_BIT 0x0004
|
|
nuclear@4
|
17 #define VDP_CTL_DT3_BIT 0x0008
|
|
nuclear@4
|
18 #define VDP_CTL_ODD_FRAME_BIT 0x0010
|
|
nuclear@4
|
19 #define VDP_CTL_COLIDE_BIT 0x0020
|
|
nuclear@4
|
20 #define VDP_CTL_SPRITE_OVF_BIT 0x0040
|
|
nuclear@4
|
21 #define VDP_CTL_FRAME_BIT 0x0080
|
|
nuclear@4
|
22 #define VDP_CTL_FIFO_FULL_BIT 0x0100
|
|
nuclear@4
|
23 #define VDP_CTL_FIFO_EMPTY_BIT 0x0200
|
|
nuclear@4
|
24
|
|
nuclear@4
|
25 /* control register write flags (RSET) */
|
|
nuclear@4
|
26 #define VDP_CTL_REGSEL_MASK 0x1f00
|
|
nuclear@4
|
27 #define VDP_CTL_DATA_MASK 0x00ff
|
|
nuclear@4
|
28
|
|
nuclear@4
|
29 #define VDP_RSET(reg, val) \
|
|
nuclear@4
|
30 (0x8000 | (VDP_CTL_REGSEL_MASK & ((uint16_t)(reg) << 8)) | \
|
|
nuclear@4
|
31 (VDP_CTL_DATA_MASK & (uint16_t)(val)))
|
|
nuclear@4
|
32
|
|
nuclear@5
|
33 #define VDP_SET_REG(reg, val) \
|
|
nuclear@5
|
34 do { VDP_PORT_CTL = VDP_RSET(reg, val); } while(0)
|
|
nuclear@5
|
35
|
|
nuclear@5
|
36 #define VDP_REG0_BASE 4
|
|
nuclear@5
|
37 #define VDP_REG0_HVCNT_BIT 0x02
|
|
nuclear@5
|
38 #define VDP_REG0_HINTR_BIT 0x10
|
|
nuclear@5
|
39
|
|
nuclear@5
|
40 #define VDP_REG1_BASE 4
|
|
nuclear@5
|
41 #define VDP_REG1_30CELL_BIT 0x08
|
|
nuclear@5
|
42 #define VDP_REG1_DMA_BIT 0x10
|
|
nuclear@5
|
43 #define VDP_REG1_VINTR_BIT 0x20
|
|
nuclear@5
|
44 #define VDP_REG1_DISP_BIT 0x40
|
|
nuclear@5
|
45
|
|
nuclear@4
|
46 #define VDP_MODE_WR_BIT 1
|
|
nuclear@4
|
47
|
|
nuclear@4
|
48 #define VDP_VRAM_WR 1
|
|
nuclear@4
|
49 #define VDP_CRAM_WR 3
|
|
nuclear@4
|
50
|
|
nuclear@4
|
51 #define VDP_ADDRSET(addr, mode) /* TODO */
|
|
nuclear@4
|
52
|
|
nuclear@5
|
53 #define VDP_CRAM_ADDR32(addr) (0xc0000000 | ((uint32_t)(addr) << 16))
|
|
nuclear@5
|
54
|
|
nuclear@5
|
55 #define VDP_SET_CRAM_ADDR(addr) \
|
|
nuclear@5
|
56 do { VDP_PORT_CTL32 = VDP_CRAM_ADDR32(addr); } while(0)
|
|
nuclear@5
|
57
|
|
nuclear@5
|
58 #define VDP_RGB24(r, g, b) \
|
|
nuclear@5
|
59 ((((uint16_t)(r) >> 4) & 0xe) | \
|
|
nuclear@5
|
60 ((uint16_t)(g) & 0xe0) | \
|
|
nuclear@5
|
61 (((uint16_t)(b) << 4) & 0xe00))
|
|
nuclear@5
|
62
|
|
nuclear@5
|
63 #define VDP_SET_CRAM_RGB24(r, g, b) \
|
|
nuclear@5
|
64 do { VDP_PORT_DATA = VDP_RGB24(r, g, b); } while(0)
|
|
nuclear@5
|
65
|
|
nuclear@5
|
66 #define VDP_SET_BGCOLOR(pal, col) \
|
|
nuclear@5
|
67 do { VDP_SET_REG(7, ((pal) << 4) | (col)); } while(0)
|
|
nuclear@4
|
68
|
|
nuclear@4
|
69 #endif /* VDP_H_ */
|
