1.1 --- a/src/vdp.h	Wed Feb 01 13:40:50 2017 +0200
     1.2 +++ b/src/vdp.h	Wed Feb 01 14:40:19 2017 +0200
     1.3 @@ -30,6 +30,19 @@
     1.4  	(0x8000 | (VDP_CTL_REGSEL_MASK & ((uint16_t)(reg) << 8)) | \
     1.5  	 (VDP_CTL_DATA_MASK & (uint16_t)(val)))
     1.6  
     1.7 +#define VDP_SET_REG(reg, val) \
     1.8 +	do { VDP_PORT_CTL = VDP_RSET(reg, val); } while(0)
     1.9 +
    1.10 +#define VDP_REG0_BASE		4
    1.11 +#define VDP_REG0_HVCNT_BIT	0x02
    1.12 +#define VDP_REG0_HINTR_BIT	0x10
    1.13 +
    1.14 +#define VDP_REG1_BASE		4
    1.15 +#define VDP_REG1_30CELL_BIT	0x08
    1.16 +#define VDP_REG1_DMA_BIT	0x10
    1.17 +#define VDP_REG1_VINTR_BIT	0x20
    1.18 +#define VDP_REG1_DISP_BIT	0x40
    1.19 +
    1.20  #define VDP_MODE_WR_BIT		1
    1.21  
    1.22  #define VDP_VRAM_WR		1
    1.23 @@ -37,5 +50,20 @@
    1.24  
    1.25  #define VDP_ADDRSET(addr, mode) /* TODO */
    1.26  
    1.27 +#define VDP_CRAM_ADDR32(addr) (0xc0000000 | ((uint32_t)(addr) << 16))
    1.28 +
    1.29 +#define VDP_SET_CRAM_ADDR(addr) \
    1.30 +	do { VDP_PORT_CTL32 = VDP_CRAM_ADDR32(addr); } while(0)
    1.31 +
    1.32 +#define VDP_RGB24(r, g, b) \
    1.33 +	((((uint16_t)(r) >> 4) & 0xe) | \
    1.34 +	 ((uint16_t)(g) & 0xe0) | \
    1.35 +	 (((uint16_t)(b) << 4) & 0xe00))
    1.36 +
    1.37 +#define VDP_SET_CRAM_RGB24(r, g, b) \
    1.38 +	do { VDP_PORT_DATA = VDP_RGB24(r, g, b); } while(0)
    1.39 +
    1.40 +#define VDP_SET_BGCOLOR(pal, col) \
    1.41 +	do { VDP_SET_REG(7, ((pal) << 4) | (col)); } while(0)
    1.42  
    1.43  #endif	/* VDP_H_ */