megadrive_test1

view src/vdp.h @ 6:862f8a034cae

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expanding the megadrive code
author John Tsiombikas <nuclear@member.fsf.org>
date Sat, 11 Feb 2017 08:56:42 +0200
parents f99eab59e7dc
children 8253942b0a1a
line source
1 #ifndef VDP_H_
2 #define VDP_H_
3
4 #include <stdint.h>
5
6 #define VDP_PORT_DATA (*(volatile uint16_t*)0xc00000)
7 #define VDP_PORT_DATA32 (*(volatile uint32_t*)0xc00000)
8 #define VDP_PORT_CTL (*(volatile uint16_t*)0xc00004)
9 #define VDP_PORT_CTL32 (*(volatile uint32_t*)0xc00004)
10 #define VDP_PORT_HVCOUNT (*(volatile uint16_t*)0xc00008)
11 #define VDP_PORT_PSG (*(volatile uint16_t*)0xc00010)
12
13 /* registers */
14 #define VDP_REG_MODE1 0
15 #define VDP_REG_MODE2 1
16 #define VDP_REG_PADDR_A 2
17 #define VDP_REG_PADDR_WIN 3
18 #define VDP_REG_PADDR_B 4
19 #define VDP_REG_SPRITE 5
20 #define VDP_REG_BGCOLOR 7
21 #define VDP_REG_HINT 10
22 #define VDP_REG_MODE3 11
23 #define VDP_REG_MODE4 12
24 #define VDP_REG_HSCROLL 13
25 #define VDP_REG_AUTOINC 15
26 #define VDP_REG_SCROLL_SIZE 16
27 #define VDP_REG_WINXPOS 17
28 #define VDP_REG_WINYPOS 18
29 #define VDP_REG_DMALEN_LOW 19
30 #define VDP_REG_DMALEN_HIGH 20
31 #define VDP_REG_DMA_SADDR_LOW 21
32 #define VDP_REG_DMA_SADDR_MID 22
33 #define VDP_REG_DMA_SADDR_HIGH 23
34
35 /* control register read flags */
36 #define VDP_CTL_PAL_BIT 0x0001
37 #define VDP_CTL_HBLANK_BIT 0x0002
38 #define VDP_CTL_VBLANK_BIT 0x0004
39 #define VDP_CTL_DT3_BIT 0x0008
40 #define VDP_CTL_ODD_FRAME_BIT 0x0010
41 #define VDP_CTL_COLIDE_BIT 0x0020
42 #define VDP_CTL_SPRITE_OVF_BIT 0x0040
43 #define VDP_CTL_FRAME_BIT 0x0080
44 #define VDP_CTL_FIFO_FULL_BIT 0x0100
45 #define VDP_CTL_FIFO_EMPTY_BIT 0x0200
46
47 /* control register write flags (RSET) */
48 #define VDP_CTL_REGSEL_MASK 0x1f00
49 #define VDP_CTL_DATA_MASK 0x00ff
50
51 #define VDP_RSET(reg, val) \
52 (0x8000 | (VDP_CTL_REGSEL_MASK & ((uint16_t)(reg) << 8)) | \
53 (VDP_CTL_DATA_MASK & (uint16_t)(val)))
54
55 #define VDP_SET_REG(reg, val) \
56 do { VDP_PORT_CTL = VDP_RSET(reg, val); } while(0)
57
58 #define VDP_REG0_BASE 4
59 #define VDP_REG0_HVCNT_BIT 0x02
60 #define VDP_REG0_HINTR_BIT 0x10
61
62 #define VDP_REG1_BASE 4
63 #define VDP_REG1_30CELL_BIT 0x08
64 #define VDP_REG1_DMA_BIT 0x10
65 #define VDP_REG1_VINTR_BIT 0x20
66 #define VDP_REG1_DISP_BIT 0x40
67 #define VDP_REG1_XVRAM_BIT 0x80
68
69 #define VDP_MODE_WR_BIT 1
70
71 #define VDP_VRAM_WR 1
72 #define VDP_CRAM_WR 3
73
74 #define VDP_DMA_MEM_TO_VRAM 0
75 #define VDP_DMA_VRAM_FILL 2
76 #define VDP_DMA_VRAM_COPY 3
77
78 #define VDP_ADDRSET(addr, mode) /* TODO */
79
80 #define VDP_CRAM_ADDR32(addr) (0xc0000000 | ((uint32_t)(addr) << 16))
81
82 #define VDP_SET_CRAM_ADDR(addr) \
83 do { VDP_PORT_CTL32 = VDP_CRAM_ADDR32(addr); } while(0)
84
85 #define VDP_RGB(r, g, b) \
86 ((((uint16_t)(r) << 1) & 0xe) | \
87 (((uint16_t)(g) << 5) & 0xe0) | \
88 (((uint16_t)(b) << 9) & 0xe00))
89
90 #define VDP_RGB24(r, g, b) \
91 ((((uint16_t)(r) >> 4) & 0xe) | \
92 ((uint16_t)(g) & 0xe0) | \
93 (((uint16_t)(b) << 4) & 0xe00))
94
95 #define VDP_SET_CRAM_RGB(r, g, b) \
96 do { VDP_PORT_DATA = VDP_RGB(r, g, b); } while(0)
97
98 #define VDP_SET_CRAM_RGB24(r, g, b) \
99 do { VDP_PORT_DATA = VDP_RGB24(r, g, b); } while(0)
100
101 #define VDP_SET_BGCOLOR(pal, col) \
102 do { VDP_SET_REG(VDP_REG_BGCOLOR, ((pal) << 4) | (col)); } while(0)
103
104 /* arguments to vdp_tilemap_slot */
105 #define VDP_PLANE_A 0
106 #define VDP_PLANE_WIN 1
107 #define VDP_PLANE_B 2
108
109 int vdp_init(void);
110 void vdp_set_tilemap_slot(int plane, int slot);
111 void *vdp_tilemap_ptr(int plane);
112 void vdp_setpal_rgb24(int idx, int r, int g, int b);
113 void vdp_setpal(int idx0, int count, unsigned char *pal);
114 /* TODO vdp_setpal_dma */
115
116 /* xtiles and ytiles can only be 32, 64, or 128 */
117 void vdp_set_scroll_size(int xtiles, int ytiles);
118
119 #endif /* VDP_H_ */