1.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.2 +++ b/src/dsregs.h	Sun Jan 28 20:05:26 2018 +0200
     1.3 @@ -0,0 +1,360 @@
     1.4 +#ifndef DSREGS_H_
     1.5 +#define DSREGS_H_
     1.6 +
     1.7 +#include <stdint.h>
     1.8 +
     1.9 +#define REG_BASE		0x4000000
    1.10 +#define REG8(x)			(*(volatile int8_t*)(REG_BASE + (x)))
    1.11 +#define REG16(x)		(*(volatile int16_t*)(REG_BASE + (x)))
    1.12 +#define REG32(x)		(*(volatile int32_t*)(REG_BASE + (x)))
    1.13 +#define REG64(x)		(*(volatile int64_t*)(REG_BASE + (x)))
    1.14 +
    1.15 +/* ---- display engine A ---- */
    1.16 +#define REG_DISPCNT		REG32(0x00)
    1.17 +#define REG_DISPSTAT	REG16(0x04)
    1.18 +#define REG_VCOUNT		REG16(0x06)
    1.19 +#define REG_BG0CNT		REG16(0x08)
    1.20 +#define REG_BG1CNT		REG16(0x0a)
    1.21 +#define REG_BG2CNT		REG16(0x0c)
    1.22 +#define REG_BG3CNT		REG16(0x0e)
    1.23 +/* scrolling registers */
    1.24 +#define REG_BG0HOFS		REG16(0x10)
    1.25 +#define REG_BG0VOFS		REG16(0x12)
    1.26 +#define REG_BG1HOFS		REG16(0x14)
    1.27 +#define REG_BG1VOFS		REG16(0x16)
    1.28 +#define REG_BG2HOFS		REG16(0x18)
    1.29 +#define REG_BG2VOFS		REG16(0x1a)
    1.30 +#define REG_BG3HOFS		REG16(0x1c)
    1.31 +#define REG_BG3VOFS		REG16(0x1e)
    1.32 +/* BG rotation and scaling registers */
    1.33 +#define REG_BG2PA		REG16(0x20)
    1.34 +#define REG_BG2PB		REG16(0x22)
    1.35 +#define REG_BG2PC		REG16(0x24)
    1.36 +#define REG_BG2PD		REG16(0x26)
    1.37 +#define REG_BG2X		REG32(0x28)
    1.38 +#define REG_BG2Y		REG32(0x2c)
    1.39 +#define REG_BG3PA		REG16(0x30)
    1.40 +#define REG_BG3PB		REG16(0x32)
    1.41 +#define REG_BG3PC		REG16(0x34)
    1.42 +#define REG_BG3PD		REG16(0x36)
    1.43 +#define REG_BG3X		REG32(0x38)
    1.44 +#define REG_BG3Y		REG32(0x3c)
    1.45 +/* window registers */
    1.46 +#define REG_WIN0H		REG16(0x40)
    1.47 +#define REG_WIN1H		REG16(0x42)
    1.48 +#define REG_WIN0V		REG16(0x44)
    1.49 +#define REG_WIN1V		REG16(0x46)
    1.50 +#define REG_WININ		REG16(0x48)
    1.51 +#define REG_WINOUT		REG16(0x4a)
    1.52 +/* mosaic */
    1.53 +#define REG_MOSAIC		REG16(0x4c)
    1.54 +/* color effects */
    1.55 +#define REG_BLDCNT		REG16(0x50)
    1.56 +#define REG_BLDALPHA	REG16(0x52)
    1.57 +#define REG_BLDY		REG16(0x54)
    1.58 +
    1.59 +#define REG_DISP3DCNT		REG16(0x60)
    1.60 +#define REG_DISPCAPCNT		REG32(0x64)
    1.61 +#define REG_DISP_MMEM_FIFO	REG32(0x68)
    1.62 +#define REG_MASTER_BRIGHT	REG16(0x6c)
    1.63 +
    1.64 +/* ---- display engine B ---- */
    1.65 +#define REG_B_DISPCNT		REG32(0x1000)
    1.66 +#define REG_B_BG0CNT		REG16(0x1008)
    1.67 +#define REG_B_BG1CNT		REG16(0x100a)
    1.68 +#define REG_B_BG2CNT		REG16(0x100c)
    1.69 +#define REG_B_BG3CNT		REG16(0x100e)
    1.70 +/* scrolling registers */
    1.71 +#define REG_B_BG0HOFS		REG16(0x1010)
    1.72 +#define REG_B_BG0VOFS		REG16(0x1012)
    1.73 +#define REG_B_BG1HOFS		REG16(0x1014)
    1.74 +#define REG_B_BG1VOFS		REG16(0x1016)
    1.75 +#define REG_B_BG2HOFS		REG16(0x1018)
    1.76 +#define REG_B_BG2VOFS		REG16(0x101a)
    1.77 +#define REG_B_BG3HOFS		REG16(0x101c)
    1.78 +#define REG_B_BG3VOFS		REG16(0x101e)
    1.79 +/* BG rotation and scaling registers */
    1.80 +#define REG_B_BG2PA			REG16(0x1020)
    1.81 +#define REG_B_BG2PB			REG16(0x1022)
    1.82 +#define REG_B_BG2PC			REG16(0x1024)
    1.83 +#define REG_B_BG2PD			REG16(0x1026)
    1.84 +#define REG_B_BG2X			REG32(0x1028)
    1.85 +#define REG_B_BG2Y			REG32(0x102c)
    1.86 +#define REG_B_BG3PA			REG16(0x1030)
    1.87 +#define REG_B_BG3PB			REG16(0x1032)
    1.88 +#define REG_B_BG3PC			REG16(0x1034)
    1.89 +#define REG_B_BG3PD			REG16(0x1036)
    1.90 +#define REG_B_BG3X			REG32(0x1038)
    1.91 +#define REG_B_BG3Y			REG32(0x103c)
    1.92 +/* window registers */
    1.93 +#define REG_B_WIN0H			REG16(0x1040)
    1.94 +#define REG_B_WIN1H			REG16(0x1042)
    1.95 +#define REG_B_WIN0V			REG16(0x1044)
    1.96 +#define REG_B_WIN1V			REG16(0x1046)
    1.97 +#define REG_B_WININ			REG16(0x1048)
    1.98 +#define REG_B_WINOUT		REG16(0x104a)
    1.99 +/* mosaic */
   1.100 +#define REG_B_MOSAIC		REG16(0x104c)
   1.101 +/* color effects */
   1.102 +#define REG_B_BLDCNT		REG16(0x1050)
   1.103 +#define REG_B_BLDALPHA		REG16(0x1052)
   1.104 +#define REG_B_BLDY			REG16(0x1054)
   1.105 +
   1.106 +#define REG_B_MASTER_BRIGHT	REG16(0x106c)
   1.107 +
   1.108 +
   1.109 +#define DISPCNT_BGMODE(x)		(x)
   1.110 +#define DISPCNT_MODE(x)			((uint32_t)(x) << 16)
   1.111 +#define DISPCNT_BG0_3D			0x00000008
   1.112 +#define DISPCNT_TILE_OBJ_1DMAP	0x00000010
   1.113 +#define DISPCNT_BM_OBJ_256X256	0x00000020
   1.114 +#define DISPCNT_BM_OBJ_1DMAP	0x00000040
   1.115 +#define DISPCNT_BLANK			0x00000080
   1.116 +#define DISPCNT_BG0				0x00000100
   1.117 +#define DISPCNT_BG1				0x00000200
   1.118 +#define DISPCNT_BG2				0x00000400
   1.119 +#define DISPCNT_BG3				0x00000800
   1.120 +#define DISPCNT_OBJ				0x00001000
   1.121 +#define DISPCNT_WIN0			0x00002000
   1.122 +#define DISPCNT_WIN1			0x00004000
   1.123 +#define DISPCNT_OBJWIN			0x00008000
   1.124 +
   1.125 +#define BGXCNT_PRIO(x)			(x)
   1.126 +#define BGXCNT_CHARBASE(x)		((x) << 2)
   1.127 +#define BGXCNT_MOSAIC			0x0040
   1.128 +#define BGXCNT_COL_256			0x0080
   1.129 +#define BGXCNT_BM				0x0080
   1.130 +#define BGXCNT_SCRBASE(x)		((x) << 8)
   1.131 +#define BGXCNT_OVF_WRAP			0x2000
   1.132 +#define BGXCNT_SCRSIZE(x)		((x) << 14)
   1.133 +#define BGXCNT_TX_256X256		BGXCNT_SCRSIZE(0)
   1.134 +#define BGXCNT_TX_512X256		BGXCNT_SCRSIZE(1)
   1.135 +#define BGXCNT_TX_256X512		BGXCNT_SCRSIZE(2)
   1.136 +#define BGXCNT_TX_512X512		BGXCNT_SCRSIZE(3)
   1.137 +#define BGXCNT_RS_128X128		BGXCNT_SCRSIZE(0)
   1.138 +#define BGXCNT_RS_256X256		BGXCNT_SCRSIZE(1)
   1.139 +#define BGXCNT_RS_512X512		BGXCNT_SCRSIZE(2)
   1.140 +#define BGXCNT_RS_1024X1024		BGXCNT_SCRSIZE(3)
   1.141 +#define BGXCNT_BM_128X128		(BGXCNT_SCRSIZE(0) | BGXCNT_BM)
   1.142 +#define BGXCNT_BM_256X256		(BGXCNT_SCRSIZE(1) | BGXCNT_BM)
   1.143 +#define BGXCNT_BM_512X256		(BGXCNT_SCRSIZE(2) | BGXCNT_BM)
   1.144 +#define BGXCNT_BM_512X512		(BGXCNT_SCRSIZE(3) | BGXCNT_BM)
   1.145 +#define BGXCNT_BM8				0
   1.146 +#define BGXCNT_BM16				0x0004
   1.147 +
   1.148 +#define VRAM_OFFSET(x)		((x) << 3)
   1.149 +#define VRAM_ENABLE			0x80
   1.150 +
   1.151 +/* ---- DMA registers ---- */
   1.152 +#define REG_DMA0SAD		REG32(0xb0)
   1.153 +#define REG_DMA0DAD		REG32(0xb4)
   1.154 +#define REG_DMA0CNT_L	REG16(0xb8)
   1.155 +#define REG_DMA0CNT_H	REG16(0xba)
   1.156 +#define REG_DMA1SAD		REG32(0xbc)
   1.157 +#define REG_DMA1DAD		REG32(0xc0)
   1.158 +#define REG_DMA1CNT_L	REG16(0xc4)
   1.159 +#define REG_DMA1CNT_H	REG16(0xc6)
   1.160 +#define REG_DMA2SAD		REG32(0xc8)
   1.161 +#define REG_DMA2DAD		REG32(0xcc)
   1.162 +#define REG_DMA2CNT_L	REG16(0xd0)
   1.163 +#define REG_DMA2CNT_H	REG16(0xd2)
   1.164 +#define REG_DMA3SAD		REG32(0xd4)
   1.165 +#define REG_DMA3DAD		REG32(0xd8)
   1.166 +#define REG_DMA3CNT_L	REG16(0xdc)
   1.167 +#define REG_DMA3CNT_H	REG16(0xde)
   1.168 +#define REG_DMA0FILL	REG32(0xe0)
   1.169 +#define REG_DMA1FILL	REG32(0xe4)
   1.170 +#define REG_DMA2FILL	REG32(0xe8)
   1.171 +#define REG_DMA3FILL	REG32(0xec)
   1.172 +
   1.173 +/* ---- timer registers ---- */
   1.174 +#define REG_TM0CNT_L	REG16(0x100)
   1.175 +#define REG_TM0CNT_H	REG16(0x102)
   1.176 +#define REG_TM1CNT_L	REG16(0x104)
   1.177 +#define REG_TM1CNT_H	REG16(0x106)
   1.178 +#define REG_TM2CNT_L	REG16(0x108)
   1.179 +#define REG_TM2CNT_H	REG16(0x10a)
   1.180 +#define REG_TM3CNT_L	REG16(0x10c)
   1.181 +#define REG_TM3CNT_H	REG16(0x10e)
   1.182 +
   1.183 +/* ---- keypad registers ---- */
   1.184 +#define REG_KEYINPUT	REG16(0x130)
   1.185 +#define REG_KEYCNT		REG16(0x132)
   1.186 +
   1.187 +/* ---- IPC/ROM registers ---- */
   1.188 +#define REG_IPCSYNC		REG16(0x180)
   1.189 +#define REG_IPCFIFOCNT	REG16(0x184)
   1.190 +#define REG_IPCFIFOSEND	REG32(0x188)
   1.191 +#define REG_AUXSPICNT	REG16(0x1a0)
   1.192 +#define REG_AUXSPIDATA	REG16(0x1a2)
   1.193 +#define REG_GCARDCNT	REG32(0x1a4)
   1.194 +#define REG_GCARDCMD64	REG64(0x1a8)
   1.195 +#define REG_GCARDSEED0	REG32(0x1b0)
   1.196 +#define REG_GCARDSEED1	REG32(0x1b4)
   1.197 +#define REG_GCARDSEED0X	REG16(0x1b8)
   1.198 +#define REG_GCARDSEED1X	REG16(0x1ba)
   1.199 +
   1.200 +/* ---- memory & IRQ control registers ---- */
   1.201 +#define REG_EXMEMCNT	REG16(0x204)
   1.202 +#define REG_IME			REG16(0x208)
   1.203 +#define REG_IE			REG32(0x210)
   1.204 +#define REG_IF			REG32(0x214)
   1.205 +#define REG_VRAMCNT_A	REG8(0x240)
   1.206 +#define REG_VRAMCNT_B	REG8(0x241)
   1.207 +#define REG_VRAMCNT_C	REG8(0x242)
   1.208 +#define REG_VRAMCNT_D	REG8(0x243)
   1.209 +#define REG_VRAMCNT_E	REG8(0x244)
   1.210 +#define REG_VRAMCNT_F	REG8(0x245)
   1.211 +#define REG_VRAMCNT_G	REG8(0x246)
   1.212 +#define REG_WRAMCNT		REG8(0x247)
   1.213 +#define REG_VRAMCNT_H	REG8(0x248)
   1.214 +#define REG_VRAMCNT_I	REG8(0x249)
   1.215 +
   1.216 +/* ---- math hardware registers ---- */
   1.217 +#define REG_DIVCNT		REG16(0x280)
   1.218 +#define REG_DIV_NUMER	REG64(0x290)
   1.219 +#define REG_DIV_DENOM	REG64(0x298)
   1.220 +#define REG_DIV_RESULT	REG64(0x2a0)
   1.221 +#define REG_DIVREM_RESULT	REG64(0x2a8)
   1.222 +#define REG_SQRTCNT		REG16(0x2b0)
   1.223 +#define REG_SQRT_RESULT	REG32(0x2b4)
   1.224 +#define REG_SQRT_PARAM	REG64(0x2b8)
   1.225 +#define REG_POSTFLG		REG32(0x300)
   1.226 +#define REG_POWCNT1		REG16(0x304)
   1.227 +#define REG_POWCNT2		REG16(0x304)
   1.228 +
   1.229 +#define POWCNT1_LCD			0x0001
   1.230 +#define POWCNT1_2DA			0x0002
   1.231 +#define POWCNT1_3DREND		0x0004
   1.232 +#define POWCNT1_3DGEOM		0x0008
   1.233 +#define POWCNT1_2DB			0x0200
   1.234 +#define POWCNT1_DSWAP		0x8000
   1.235 +
   1.236 +#define POWCNT2_SOUND		0x0001
   1.237 +#define POWCNT2_WIFI		0x0002
   1.238 +
   1.239 +/* ---- sound registers ---- */
   1.240 +#define REG_SOUNDXCNT(x)	REG32(0x400 | ((x) << 4))
   1.241 +#define REG_SOUNDXSAD(x)	REG32(0x404 | ((x) << 4))
   1.242 +#define REG_SOUNDXTMR(x)	REG32(0x408 | ((x) << 4))
   1.243 +#define REG_SOUNDXPNT(x)	REG32(0x40a | ((x) << 4))
   1.244 +#define REG_SOUNDXLEN(x)	REG32(0x40c | ((x) << 4))
   1.245 +#define REG_SOUNDCNT		REG32(0x500)
   1.246 +#define REG_SOUNDBIAS		REG32(0x504)
   1.247 +
   1.248 +/* ---- 3D hardware registers ---- */
   1.249 +/* rendering engine */
   1.250 +#define REG_RDLINES_COUNR	REG8(0x320)
   1.251 +#define REG_EDGE_COLOR0		REG16(0x330)
   1.252 +#define REG_EDGE_COLOR1		REG16(0x332)
   1.253 +#define REG_EDGE_COLOR2		REG16(0x334)
   1.254 +#define REG_EDGE_COLOR3		REG16(0x336)
   1.255 +#define REG_EDGE_COLOR4		REG16(0x338)
   1.256 +#define REG_EDGE_COLOR5		REG16(0x33a)
   1.257 +#define REG_EDGE_COLOR6		REG16(0x33c)
   1.258 +#define REG_EDGE_COLOR7		REG16(0x33e)
   1.259 +#define REG_ALPHA_TEST_REF	REG8(0x340)
   1.260 +#define REG_CLEAR_COLOR		REG32(0x350)
   1.261 +#define REG_CLEAR_DEPTH		REG16(0x354)
   1.262 +#define REG_CLRIMAGE_OFFSET	REG16(0x356)
   1.263 +#define REG_FOG_COLOR		REG32(0x358)
   1.264 +#define REG_FOG_OFFSET		REG16(0x35c)
   1.265 +#define FOG_TABLE_ADDR		((uint8_t*)(REG_BASE + 0x360))
   1.266 +#define TOON_TABLE_ADDR		((uint16_t*)(REG_BASE + 0x380))
   1.267 +/* geometry engine */
   1.268 +#define GXFIFO_ADDR			((uint8_t*)(REG_BASE + 0x400))
   1.269 +#define REG_GXSTAT			REG32(0x600)
   1.270 +#define REG_RAM_COUNT		REG32(0x604)
   1.271 +#define REG_DISP_1DOT_DEPTH	REG16(0x610)
   1.272 +#define POS_RESULT_ADDR		((uint8_t*)(REG_BASE + 0x620))
   1.273 +#define VEC_RESULT_ADDR		((uint8_t*)(REG_BASE + 0x630))
   1.274 +#define CLIPMTX_RESULT_ADDR	((uint32_t*)(REG_BASE + 0x640))
   1.275 +#define VECMTX_RESULT_ADDR	((uint32_t*)(REG_BASE + 0x680))
   1.276 +/* geometry command ports */
   1.277 +#define REG_MTX_MODE		REG32(0x440)	/* 1 */
   1.278 +#define REG_MTX_PUSH		REG32(0x444)	/* 0 */
   1.279 +#define REG_MTX_POP			REG32(0x448)	/* 1 */
   1.280 +#define REG_MTX_STORE		REG32(0x44c)	/* 1 */
   1.281 +#define REG_MTX_RESTORE		REG32(0x450)	/* 1 */
   1.282 +#define REG_MTX_IDENTITY	REG32(0x454)	/* 0 */
   1.283 +#define REG_MTX_LOAD_4X4	REG32(0x458)	/* 16 */
   1.284 +#define REG_MTX_LOAD_4X3	REG32(0x45c)	/* 12 */
   1.285 +#define REG_MTX_MULT_4X4	REG32(0x460)	/* 16 */
   1.286 +#define REG_MTX_MULT_4X3	REG32(0x464)	/* 12 */
   1.287 +#define REG_MTX_MULT_3X3	REG32(0x468)	/* 9 */
   1.288 +#define REG_MTX_SCALE		REG32(0x46c)	/* 3 */
   1.289 +#define REG_MTX_TRANS		REG32(0x470)	/* 3 */
   1.290 +#define REG_COLOR			REG32(0x480)	/* 1 */
   1.291 +#define REG_NORMAL			REG32(0x484)	/* 1 */
   1.292 +#define REG_TEXCOORD		REG32(0x488)	/* 1 */
   1.293 +#define REG_VTX_16			REG32(0x48c)	/* 2 */
   1.294 +#define REG_VTX_10			REG32(0x490)	/* 1 */
   1.295 +#define REG_VTX_XY			REG32(0x494)	/* 1 */
   1.296 +#define REG_VTX_XZ			REG32(0x498)	/* 1 */
   1.297 +#define REG_VTX_YZ			REG32(0x49c)	/* 1 */
   1.298 +#define REG_VTX_DIFF		REG32(0x4a0)	/* 1 */
   1.299 +#define REG_POLYGON_ATTR	REG32(0x4a4)	/* 1 */
   1.300 +#define REG_TEXIMAGE_PARAM	REG32(0x4a8)	/* 1 */
   1.301 +#define REG_PLTT_BASE		REG32(0x4ac)	/* 1 */
   1.302 +#define REG_DIF_AMB			REG32(0x4c0)	/* 1 */
   1.303 +#define REG_SPE_EMI			REG32(0x4c4)	/* 1 */
   1.304 +#define REG_LIGHT_VECTOR	REG32(0x4c8)	/* 1 */
   1.305 +#define REG_LIGHT_COLOR		REG32(0x4cc)	/* 1 */
   1.306 +#define REG_SHININESS		REG32(0x4d0)	/* 32 */
   1.307 +#define REG_BEGIN_VTXS		REG32(0x500)	/* 1 */
   1.308 +#define REG_END_VTXS		REG32(0x504)	/* 0 */
   1.309 +#define REG_SWAP_BUFFERS	REG32(0x540)	/* 1 */
   1.310 +#define REG_VIEWPORT		REG32(0x580)	/* 1 */
   1.311 +#define REG_BOX_TEST		REG32(0x5c0)	/* 3 */
   1.312 +#define REG_POS_TEST		REG32(0x5c4)	/* 2 */
   1.313 +#define REG_VEC_TEST		REG32(0x5c8)	/* 1 */
   1.314 +
   1.315 +/* geometry commands */
   1.316 +#define GCMD_MTX_MODE		0x10	/* 1 */
   1.317 +#define GCMD_MTX_PUSH		0x11	/* 0 */
   1.318 +#define GCMD_MTX_POP		0x12	/* 1 */
   1.319 +#define GCMD_MTX_STORE		0x13	/* 1 */
   1.320 +#define GCMD_MTX_RESTORE	0x14	/* 1 */
   1.321 +#define GCMD_MTX_IDENTITY	0x15	/* 0 */
   1.322 +#define GCMD_MTX_LOAD_4X4	0x16	/* 16 */
   1.323 +#define GCMD_MTX_LOAD_4X3	0x17	/* 12 */
   1.324 +#define GCMD_MTX_MULT_4X4	0x18	/* 16 */
   1.325 +#define GCMD_MTX_MULT_4X3	0x19	/* 12 */
   1.326 +#define GCMD_MTX_MULT_3X3	0x1a	/* 9 */
   1.327 +#define GCMD_MTX_SCALE		0x1b	/* 3 */
   1.328 +#define GCMD_MTX_TRANS		0x1c	/* 3 */
   1.329 +#define GCMD_COLOR			0x20	/* 1 */
   1.330 +#define GCMD_NORMAL			0x21	/* 1 */
   1.331 +#define GCMD_TEXCOORD		0x22	/* 1 */
   1.332 +#define GCMD_VTX_16			0x23	/* 2 */
   1.333 +#define GCMD_VTX_10			0x24	/* 1 */
   1.334 +#define GCMD_VTX_XY			0x25	/* 1 */
   1.335 +#define GCMD_VTX_XZ			0x26	/* 1 */
   1.336 +#define GCMD_VTX_YZ			0x27	/* 1 */
   1.337 +#define GCMD_VTX_DIFF		0x28	/* 1 */
   1.338 +#define GCMD_POLYGON_ATTR	0x29	/* 1 */
   1.339 +#define GCMD_TEXIMAGE_PARAM	0x2a	/* 1 */
   1.340 +#define GCMD_PLTT_BASE		0x2b	/* 1 */
   1.341 +#define GCMD_DIF_AMB		0x30	/* 1 */
   1.342 +#define GCMD_SPE_EMI		0x31	/* 1 */
   1.343 +#define GCMD_LIGHT_VECTOR	0x32	/* 1 */
   1.344 +#define GCMD_LIGHT_COLOR	0x33	/* 1 */
   1.345 +#define GCMD_SHININESS		0x34	/* 32 */
   1.346 +#define GCMD_BEGIN_VTXS		0x40	/* 1 */
   1.347 +#define GCMD_END_VTXS		0x41	/* 0 */
   1.348 +#define GCMD_SWAP_BUFFERS	0x50	/* 1 */
   1.349 +#define GCMD_VIEWPORT		0x60	/* 1 */
   1.350 +#define GCMD_BOX_TEST		0x70	/* 3 */
   1.351 +#define GCMD_POS_TEST		0x71	/* 2 */
   1.352 +#define GCMD_VEC_TEST		0x72	/* 1 */
   1.353 +
   1.354 +/* addresses of interest */
   1.355 +#define SHARED_WRAM_PTR		((void*)0x3000000)
   1.356 +#define VRAM_BGA_PTR		((void*)0x6000000)
   1.357 +#define VRAM_BGB_PTR		((void*)0x6200000)
   1.358 +#define VRAM_OBJA_PTR		((void*)0x6400000)
   1.359 +#define VRAM_OBJB_PTR		((void*)0x6600000)
   1.360 +#define VRAM_LCDC_PTR		((void*)0x6800000)
   1.361 +#define OAM_PTR				((void*)0x7000000)
   1.362 +
   1.363 +#endif	/* DSREGS_H_ */