nds_test2
view src/dsregs.h @ 2:dd8c9847bae9
cube
| author | John Tsiombikas <nuclear@member.fsf.org> |
|---|---|
| date | Mon, 29 Jan 2018 14:40:45 +0200 |
| parents | abcaf667f2bd |
| children |
line source
1 #ifndef DSREGS_H_
2 #define DSREGS_H_
4 #include <stdint.h>
6 #define REG_BASE 0x4000000
7 #define REG8(x) (*(volatile int8_t*)(REG_BASE + (x)))
8 #define REG16(x) (*(volatile int16_t*)(REG_BASE + (x)))
9 #define REG32(x) (*(volatile int32_t*)(REG_BASE + (x)))
10 #define REG64(x) (*(volatile int64_t*)(REG_BASE + (x)))
12 /* ---- display engine A ---- */
13 #define REG_DISPCNT REG32(0x00)
14 #define REG_DISPSTAT REG16(0x04)
15 #define REG_VCOUNT REG16(0x06)
16 #define REG_BG0CNT REG16(0x08)
17 #define REG_BG1CNT REG16(0x0a)
18 #define REG_BG2CNT REG16(0x0c)
19 #define REG_BG3CNT REG16(0x0e)
20 /* scrolling registers */
21 #define REG_BG0HOFS REG16(0x10)
22 #define REG_BG0VOFS REG16(0x12)
23 #define REG_BG1HOFS REG16(0x14)
24 #define REG_BG1VOFS REG16(0x16)
25 #define REG_BG2HOFS REG16(0x18)
26 #define REG_BG2VOFS REG16(0x1a)
27 #define REG_BG3HOFS REG16(0x1c)
28 #define REG_BG3VOFS REG16(0x1e)
29 /* BG rotation and scaling registers */
30 #define REG_BG2PA REG16(0x20)
31 #define REG_BG2PB REG16(0x22)
32 #define REG_BG2PC REG16(0x24)
33 #define REG_BG2PD REG16(0x26)
34 #define REG_BG2X REG32(0x28)
35 #define REG_BG2Y REG32(0x2c)
36 #define REG_BG3PA REG16(0x30)
37 #define REG_BG3PB REG16(0x32)
38 #define REG_BG3PC REG16(0x34)
39 #define REG_BG3PD REG16(0x36)
40 #define REG_BG3X REG32(0x38)
41 #define REG_BG3Y REG32(0x3c)
42 /* window registers */
43 #define REG_WIN0H REG16(0x40)
44 #define REG_WIN1H REG16(0x42)
45 #define REG_WIN0V REG16(0x44)
46 #define REG_WIN1V REG16(0x46)
47 #define REG_WININ REG16(0x48)
48 #define REG_WINOUT REG16(0x4a)
49 /* mosaic */
50 #define REG_MOSAIC REG16(0x4c)
51 /* color effects */
52 #define REG_BLDCNT REG16(0x50)
53 #define REG_BLDALPHA REG16(0x52)
54 #define REG_BLDY REG16(0x54)
56 #define REG_DISP3DCNT REG16(0x60)
57 #define REG_DISPCAPCNT REG32(0x64)
58 #define REG_DISP_MMEM_FIFO REG32(0x68)
59 #define REG_MASTER_BRIGHT REG16(0x6c)
61 /* ---- display engine B ---- */
62 #define REG_B_DISPCNT REG32(0x1000)
63 #define REG_B_BG0CNT REG16(0x1008)
64 #define REG_B_BG1CNT REG16(0x100a)
65 #define REG_B_BG2CNT REG16(0x100c)
66 #define REG_B_BG3CNT REG16(0x100e)
67 /* scrolling registers */
68 #define REG_B_BG0HOFS REG16(0x1010)
69 #define REG_B_BG0VOFS REG16(0x1012)
70 #define REG_B_BG1HOFS REG16(0x1014)
71 #define REG_B_BG1VOFS REG16(0x1016)
72 #define REG_B_BG2HOFS REG16(0x1018)
73 #define REG_B_BG2VOFS REG16(0x101a)
74 #define REG_B_BG3HOFS REG16(0x101c)
75 #define REG_B_BG3VOFS REG16(0x101e)
76 /* BG rotation and scaling registers */
77 #define REG_B_BG2PA REG16(0x1020)
78 #define REG_B_BG2PB REG16(0x1022)
79 #define REG_B_BG2PC REG16(0x1024)
80 #define REG_B_BG2PD REG16(0x1026)
81 #define REG_B_BG2X REG32(0x1028)
82 #define REG_B_BG2Y REG32(0x102c)
83 #define REG_B_BG3PA REG16(0x1030)
84 #define REG_B_BG3PB REG16(0x1032)
85 #define REG_B_BG3PC REG16(0x1034)
86 #define REG_B_BG3PD REG16(0x1036)
87 #define REG_B_BG3X REG32(0x1038)
88 #define REG_B_BG3Y REG32(0x103c)
89 /* window registers */
90 #define REG_B_WIN0H REG16(0x1040)
91 #define REG_B_WIN1H REG16(0x1042)
92 #define REG_B_WIN0V REG16(0x1044)
93 #define REG_B_WIN1V REG16(0x1046)
94 #define REG_B_WININ REG16(0x1048)
95 #define REG_B_WINOUT REG16(0x104a)
96 /* mosaic */
97 #define REG_B_MOSAIC REG16(0x104c)
98 /* color effects */
99 #define REG_B_BLDCNT REG16(0x1050)
100 #define REG_B_BLDALPHA REG16(0x1052)
101 #define REG_B_BLDY REG16(0x1054)
103 #define REG_B_MASTER_BRIGHT REG16(0x106c)
106 #define DISPCNT_BGMODE(x) (x)
107 #define DISPCNT_MODE(x) ((uint32_t)(x) << 16)
108 #define DISPCNT_BG0_3D 0x00000008
109 #define DISPCNT_TILE_OBJ_1DMAP 0x00000010
110 #define DISPCNT_BM_OBJ_256X256 0x00000020
111 #define DISPCNT_BM_OBJ_1DMAP 0x00000040
112 #define DISPCNT_BLANK 0x00000080
113 #define DISPCNT_BG0 0x00000100
114 #define DISPCNT_BG1 0x00000200
115 #define DISPCNT_BG2 0x00000400
116 #define DISPCNT_BG3 0x00000800
117 #define DISPCNT_OBJ 0x00001000
118 #define DISPCNT_WIN0 0x00002000
119 #define DISPCNT_WIN1 0x00004000
120 #define DISPCNT_OBJWIN 0x00008000
122 #define BGXCNT_PRIO(x) (x)
123 #define BGXCNT_CHARBASE(x) ((x) << 2)
124 #define BGXCNT_MOSAIC 0x0040
125 #define BGXCNT_COL_256 0x0080
126 #define BGXCNT_BM 0x0080
127 #define BGXCNT_SCRBASE(x) ((x) << 8)
128 #define BGXCNT_OVF_WRAP 0x2000
129 #define BGXCNT_SCRSIZE(x) ((x) << 14)
130 #define BGXCNT_TX_256X256 BGXCNT_SCRSIZE(0)
131 #define BGXCNT_TX_512X256 BGXCNT_SCRSIZE(1)
132 #define BGXCNT_TX_256X512 BGXCNT_SCRSIZE(2)
133 #define BGXCNT_TX_512X512 BGXCNT_SCRSIZE(3)
134 #define BGXCNT_RS_128X128 BGXCNT_SCRSIZE(0)
135 #define BGXCNT_RS_256X256 BGXCNT_SCRSIZE(1)
136 #define BGXCNT_RS_512X512 BGXCNT_SCRSIZE(2)
137 #define BGXCNT_RS_1024X1024 BGXCNT_SCRSIZE(3)
138 #define BGXCNT_BM_128X128 (BGXCNT_SCRSIZE(0) | BGXCNT_BM)
139 #define BGXCNT_BM_256X256 (BGXCNT_SCRSIZE(1) | BGXCNT_BM)
140 #define BGXCNT_BM_512X256 (BGXCNT_SCRSIZE(2) | BGXCNT_BM)
141 #define BGXCNT_BM_512X512 (BGXCNT_SCRSIZE(3) | BGXCNT_BM)
142 #define BGXCNT_BM8 0
143 #define BGXCNT_BM16 0x0004
145 #define VRAM_OFFSET(x) ((x) << 3)
146 #define VRAM_ENABLE 0x80
148 /* ---- DMA registers ---- */
149 #define REG_DMA0SAD REG32(0xb0)
150 #define REG_DMA0DAD REG32(0xb4)
151 #define REG_DMA0CNT_L REG16(0xb8)
152 #define REG_DMA0CNT_H REG16(0xba)
153 #define REG_DMA1SAD REG32(0xbc)
154 #define REG_DMA1DAD REG32(0xc0)
155 #define REG_DMA1CNT_L REG16(0xc4)
156 #define REG_DMA1CNT_H REG16(0xc6)
157 #define REG_DMA2SAD REG32(0xc8)
158 #define REG_DMA2DAD REG32(0xcc)
159 #define REG_DMA2CNT_L REG16(0xd0)
160 #define REG_DMA2CNT_H REG16(0xd2)
161 #define REG_DMA3SAD REG32(0xd4)
162 #define REG_DMA3DAD REG32(0xd8)
163 #define REG_DMA3CNT_L REG16(0xdc)
164 #define REG_DMA3CNT_H REG16(0xde)
165 #define REG_DMA0FILL REG32(0xe0)
166 #define REG_DMA1FILL REG32(0xe4)
167 #define REG_DMA2FILL REG32(0xe8)
168 #define REG_DMA3FILL REG32(0xec)
170 /* ---- timer registers ---- */
171 #define REG_TM0CNT_L REG16(0x100)
172 #define REG_TM0CNT_H REG16(0x102)
173 #define REG_TM1CNT_L REG16(0x104)
174 #define REG_TM1CNT_H REG16(0x106)
175 #define REG_TM2CNT_L REG16(0x108)
176 #define REG_TM2CNT_H REG16(0x10a)
177 #define REG_TM3CNT_L REG16(0x10c)
178 #define REG_TM3CNT_H REG16(0x10e)
180 /* ---- keypad registers ---- */
181 #define REG_KEYINPUT REG16(0x130)
182 #define REG_KEYCNT REG16(0x132)
184 /* ---- IPC/ROM registers ---- */
185 #define REG_IPCSYNC REG16(0x180)
186 #define REG_IPCFIFOCNT REG16(0x184)
187 #define REG_IPCFIFOSEND REG32(0x188)
188 #define REG_AUXSPICNT REG16(0x1a0)
189 #define REG_AUXSPIDATA REG16(0x1a2)
190 #define REG_GCARDCNT REG32(0x1a4)
191 #define REG_GCARDCMD64 REG64(0x1a8)
192 #define REG_GCARDSEED0 REG32(0x1b0)
193 #define REG_GCARDSEED1 REG32(0x1b4)
194 #define REG_GCARDSEED0X REG16(0x1b8)
195 #define REG_GCARDSEED1X REG16(0x1ba)
197 /* ---- memory & IRQ control registers ---- */
198 #define REG_EXMEMCNT REG16(0x204)
199 #define REG_IME REG16(0x208)
200 #define REG_IE REG32(0x210)
201 #define REG_IF REG32(0x214)
202 #define REG_VRAMCNT_A REG8(0x240)
203 #define REG_VRAMCNT_B REG8(0x241)
204 #define REG_VRAMCNT_C REG8(0x242)
205 #define REG_VRAMCNT_D REG8(0x243)
206 #define REG_VRAMCNT_E REG8(0x244)
207 #define REG_VRAMCNT_F REG8(0x245)
208 #define REG_VRAMCNT_G REG8(0x246)
209 #define REG_WRAMCNT REG8(0x247)
210 #define REG_VRAMCNT_H REG8(0x248)
211 #define REG_VRAMCNT_I REG8(0x249)
213 /* ---- math hardware registers ---- */
214 #define REG_DIVCNT REG32(0x280)
215 #define REG_DIV_NUMER REG64(0x290)
216 #define REG_DIV_NUMERL REG32(0x290)
217 #define REG_DIV_NUMERH REG32(0x294)
218 #define REG_DIV_DENOM REG64(0x298)
219 #define REG_DIV_DENOML REG32(0x298)
220 #define REG_DIV_DENOMH REG32(0x29c)
221 #define REG_DIV_RESULT REG64(0x2a0)
222 #define REG_DIV_RESULTL REG32(0x2a0)
223 #define REG_DIV_RESULTH REG32(0x2a4)
224 #define REG_DIVREM_RESULT REG64(0x2a8)
225 #define REG_DIVREM_RESULTL REG32(0x2a8)
226 #define REG_DIVREM_RESULTH REG32(0x2ac)
227 #define REG_SQRTCNT REG16(0x2b0)
228 #define REG_SQRT_RESULT REG32(0x2b4)
229 #define REG_SQRT_PARAM REG64(0x2b8)
230 #define REG_POSTFLG REG32(0x300)
231 #define REG_POWCNT1 REG16(0x304)
232 #define REG_POWCNT2 REG16(0x304)
234 #define DIVCNT_32_32 0
235 #define DIVCNT_64_32 1
236 #define DIVCNT_64_64 2
237 #define DIVCNT_DIV0 0x4000
238 #define DIVCNT_BUSY 0x8000
240 #define POWCNT1_LCD 0x0001
241 #define POWCNT1_2DA 0x0002
242 #define POWCNT1_3DREND 0x0004
243 #define POWCNT1_3DGEOM 0x0008
244 #define POWCNT1_2DB 0x0200
245 #define POWCNT1_DSWAP 0x8000
247 #define POWCNT2_SOUND 0x0001
248 #define POWCNT2_WIFI 0x0002
250 /* ---- sound registers ---- */
251 #define REG_SOUNDXCNT(x) REG32(0x400 | ((x) << 4))
252 #define REG_SOUNDXSAD(x) REG32(0x404 | ((x) << 4))
253 #define REG_SOUNDXTMR(x) REG32(0x408 | ((x) << 4))
254 #define REG_SOUNDXPNT(x) REG32(0x40a | ((x) << 4))
255 #define REG_SOUNDXLEN(x) REG32(0x40c | ((x) << 4))
256 #define REG_SOUNDCNT REG32(0x500)
257 #define REG_SOUNDBIAS REG32(0x504)
259 /* ---- 3D hardware registers ---- */
260 /* rendering engine */
261 #define REG_RDLINES_COUNR REG8(0x320)
262 #define REG_EDGE_COLOR0 REG16(0x330)
263 #define REG_EDGE_COLOR1 REG16(0x332)
264 #define REG_EDGE_COLOR2 REG16(0x334)
265 #define REG_EDGE_COLOR3 REG16(0x336)
266 #define REG_EDGE_COLOR4 REG16(0x338)
267 #define REG_EDGE_COLOR5 REG16(0x33a)
268 #define REG_EDGE_COLOR6 REG16(0x33c)
269 #define REG_EDGE_COLOR7 REG16(0x33e)
270 #define REG_ALPHA_TEST_REF REG8(0x340)
271 #define REG_CLEAR_COLOR REG32(0x350)
272 #define REG_CLEAR_DEPTH REG16(0x354)
273 #define REG_CLRIMAGE_OFFSET REG16(0x356)
274 #define REG_FOG_COLOR REG32(0x358)
275 #define REG_FOG_OFFSET REG16(0x35c)
276 #define FOG_TABLE_ADDR ((uint8_t*)(REG_BASE + 0x360))
277 #define TOON_TABLE_ADDR ((uint16_t*)(REG_BASE + 0x380))
278 /* geometry engine */
279 #define GXFIFO_ADDR ((uint8_t*)(REG_BASE + 0x400))
280 #define REG_GXSTAT REG32(0x600)
281 #define REG_RAM_COUNT REG32(0x604)
282 #define REG_DISP_1DOT_DEPTH REG16(0x610)
283 #define POS_RESULT_ADDR ((uint8_t*)(REG_BASE + 0x620))
284 #define VEC_RESULT_ADDR ((uint8_t*)(REG_BASE + 0x630))
285 #define CLIPMTX_RESULT_ADDR ((uint32_t*)(REG_BASE + 0x640))
286 #define VECMTX_RESULT_ADDR ((uint32_t*)(REG_BASE + 0x680))
287 /* geometry command ports */
288 #define REG_MTX_MODE REG32(0x440) /* 1 */
289 #define REG_MTX_PUSH REG32(0x444) /* 0 */
290 #define REG_MTX_POP REG32(0x448) /* 1 */
291 #define REG_MTX_STORE REG32(0x44c) /* 1 */
292 #define REG_MTX_RESTORE REG32(0x450) /* 1 */
293 #define REG_MTX_IDENTITY REG32(0x454) /* 0 */
294 #define REG_MTX_LOAD_4X4 REG32(0x458) /* 16 */
295 #define REG_MTX_LOAD_4X3 REG32(0x45c) /* 12 */
296 #define REG_MTX_MULT_4X4 REG32(0x460) /* 16 */
297 #define REG_MTX_MULT_4X3 REG32(0x464) /* 12 */
298 #define REG_MTX_MULT_3X3 REG32(0x468) /* 9 */
299 #define REG_MTX_SCALE REG32(0x46c) /* 3 */
300 #define REG_MTX_TRANS REG32(0x470) /* 3 */
301 #define REG_COLOR REG32(0x480) /* 1 */
302 #define REG_NORMAL REG32(0x484) /* 1 */
303 #define REG_TEXCOORD REG32(0x488) /* 1 */
304 #define REG_VTX_16 REG32(0x48c) /* 2 */
305 #define REG_VTX_10 REG32(0x490) /* 1 */
306 #define REG_VTX_XY REG32(0x494) /* 1 */
307 #define REG_VTX_XZ REG32(0x498) /* 1 */
308 #define REG_VTX_YZ REG32(0x49c) /* 1 */
309 #define REG_VTX_DIFF REG32(0x4a0) /* 1 */
310 #define REG_POLYGON_ATTR REG32(0x4a4) /* 1 */
311 #define REG_TEXIMAGE_PARAM REG32(0x4a8) /* 1 */
312 #define REG_PLTT_BASE REG32(0x4ac) /* 1 */
313 #define REG_DIF_AMB REG32(0x4c0) /* 1 */
314 #define REG_SPE_EMI REG32(0x4c4) /* 1 */
315 #define REG_LIGHT_VECTOR REG32(0x4c8) /* 1 */
316 #define REG_LIGHT_COLOR REG32(0x4cc) /* 1 */
317 #define REG_SHININESS REG32(0x4d0) /* 32 */
318 #define REG_BEGIN_VTXS REG32(0x500) /* 1 */
319 #define REG_END_VTXS REG32(0x504) /* 0 */
320 #define REG_SWAP_BUFFERS REG32(0x540) /* 1 */
321 #define REG_VIEWPORT REG32(0x580) /* 1 */
322 #define REG_BOX_TEST REG32(0x5c0) /* 3 */
323 #define REG_POS_TEST REG32(0x5c4) /* 2 */
324 #define REG_VEC_TEST REG32(0x5c8) /* 1 */
326 /* geometry commands */
327 #define GCMD_MTX_MODE 0x10 /* 1 */
328 #define GCMD_MTX_PUSH 0x11 /* 0 */
329 #define GCMD_MTX_POP 0x12 /* 1 */
330 #define GCMD_MTX_STORE 0x13 /* 1 */
331 #define GCMD_MTX_RESTORE 0x14 /* 1 */
332 #define GCMD_MTX_IDENTITY 0x15 /* 0 */
333 #define GCMD_MTX_LOAD_4X4 0x16 /* 16 */
334 #define GCMD_MTX_LOAD_4X3 0x17 /* 12 */
335 #define GCMD_MTX_MULT_4X4 0x18 /* 16 */
336 #define GCMD_MTX_MULT_4X3 0x19 /* 12 */
337 #define GCMD_MTX_MULT_3X3 0x1a /* 9 */
338 #define GCMD_MTX_SCALE 0x1b /* 3 */
339 #define GCMD_MTX_TRANS 0x1c /* 3 */
340 #define GCMD_COLOR 0x20 /* 1 */
341 #define GCMD_NORMAL 0x21 /* 1 */
342 #define GCMD_TEXCOORD 0x22 /* 1 */
343 #define GCMD_VTX_16 0x23 /* 2 */
344 #define GCMD_VTX_10 0x24 /* 1 */
345 #define GCMD_VTX_XY 0x25 /* 1 */
346 #define GCMD_VTX_XZ 0x26 /* 1 */
347 #define GCMD_VTX_YZ 0x27 /* 1 */
348 #define GCMD_VTX_DIFF 0x28 /* 1 */
349 #define GCMD_POLYGON_ATTR 0x29 /* 1 */
350 #define GCMD_TEXIMAGE_PARAM 0x2a /* 1 */
351 #define GCMD_PLTT_BASE 0x2b /* 1 */
352 #define GCMD_DIF_AMB 0x30 /* 1 */
353 #define GCMD_SPE_EMI 0x31 /* 1 */
354 #define GCMD_LIGHT_VECTOR 0x32 /* 1 */
355 #define GCMD_LIGHT_COLOR 0x33 /* 1 */
356 #define GCMD_SHININESS 0x34 /* 32 */
357 #define GCMD_BEGIN_VTXS 0x40 /* 1 */
358 #define GCMD_END_VTXS 0x41 /* 0 */
359 #define GCMD_SWAP_BUFFERS 0x50 /* 1 */
360 #define GCMD_VIEWPORT 0x60 /* 1 */
361 #define GCMD_BOX_TEST 0x70 /* 3 */
362 #define GCMD_POS_TEST 0x71 /* 2 */
363 #define GCMD_VEC_TEST 0x72 /* 1 */
365 /* addresses of interest */
366 #define SHARED_WRAM_PTR ((void*)0x3000000)
367 #define VRAM_BGA_PTR ((void*)0x6000000)
368 #define VRAM_BGB_PTR ((void*)0x6200000)
369 #define VRAM_OBJA_PTR ((void*)0x6400000)
370 #define VRAM_OBJB_PTR ((void*)0x6600000)
371 #define VRAM_LCDC_PTR ((void*)0x6800000)
372 #define OAM_PTR ((void*)0x7000000)
374 #endif /* DSREGS_H_ */