megadrive_test2

view src/main.c @ 12:54caa2b214ca

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TMSS code
author John Tsiombikas <nuclear@member.fsf.org>
date Wed, 26 Dec 2018 04:39:09 +0200
parents 6ecf2f3ff05a
children
line source
1 #include <stdint.h>
2 #include "vdp.h"
3 #include "io.h"
4 #include "pad.h"
5 #include "intr.h"
6 #include "debug.h"
7 #include "tun_data.h"
8
9 #define NAMETAB_A 6
10 #define NAMETAB_B 6
11
12 void load_pattern(int idx, void *data);
13 void set_tile(int nametab_idx, int x, int y, int tile_idx, int palidx);
14
15 #define CYCLE_BEG 1
16 #define CYCLE_END 14
17 static uint16_t pal[16] = {
18 VDP_PACK_RGB(0, 0, 0), /* 0: fixed */
19 VDP_PACK_RGB(0, 0, 0), /* 1: cycle start */
20 VDP_PACK_RGB(0, 0, 0), VDP_PACK_RGB(0, 0, 0),
21 VDP_PACK_RGB(0, 0, 0), VDP_PACK_RGB(0, 0, 0),
22 VDP_PACK_RGB(0, 0, 0), VDP_PACK_RGB(0, 0, 0),
23 VDP_PACK_RGB(0, 0, 0), VDP_PACK_RGB(0, 0, 0),
24 VDP_PACK_RGB(0, 0, 0), VDP_PACK_RGB(0, 0, 0),
25 VDP_PACK_RGB(0, 0, 0), /* 12: \ */
26 VDP_PACK_RGB(7, 0, 3), /* 13: > beam */
27 VDP_PACK_RGB(0, 0, 0), /* 14: / cycle end */
28 VDP_PACK_RGB(7, 0, 3) /* 15: fixed */
29 };
30
31 static uint16_t dbg;
32
33
34 int main(void)
35 {
36 int i, j;
37
38 vdp_init();
39 io_init();
40 dbg_init();
41
42 if(IO_REG_VER & IO_VER_PAL) {
43 vdp_setreg(VDP_REG_MODE2, vdp_getreg(VDP_REG_MODE2) | VDP_MODE2_V30CELL);
44 }
45
46 vdp_begin_palette(0, 0);
47 for(i=0; i<16; i++) {
48 VDP_PORT_DATA = pal[i];
49 }
50
51 for(i=0; i<tun_xtiles * tun_ytiles; i++) {
52 load_pattern(i, tun_tiles[i]);
53 }
54
55 vdp_set_nametab_idx(VDP_PLANE_A, NAMETAB_A);
56 vdp_set_nametab_idx(VDP_PLANE_B, NAMETAB_B);
57
58 for(i=0; i<tun_ytiles; i++) {
59 for(j=0; j<tun_xtiles; j++) {
60 set_tile(NAMETAB_A, j, i, i * tun_xtiles + j, 0);
61 }
62 }
63
64 //vdp_enable_hintr(12);
65 vdp_enable_vintr();
66
67 for(;;) {
68 pad_update(0);
69
70 if(pad_pressed(0, IO_PAD_C)) {
71 disable_intr();
72 vdp_setreg(VDP_REG_MODE2, vdp_getreg(VDP_REG_MODE2) ^ VDP_MODE2_V30CELL);
73 vdp_set_bgcolor(DBG_PALIDX, ++dbg & 1);
74 enable_intr();
75 }
76
77 vdp_wait_vblank();
78 }
79
80 return 0;
81 }
82
83 void load_pattern(int idx, void *data)
84 {
85 int i;
86 uint32_t *ptr = data;
87 uint16_t addr = idx << 5;
88 vdp_setup_access(addr, VDP_MEM_WRITE, VDP_MEM_VRAM);
89
90 for(i=0; i<16; i++) {
91 VDP_PORT_DATA32 = *ptr++;
92 }
93 }
94
95 void set_tile(int nametab_idx, int x, int y, int tile_idx, int palidx)
96 {
97 uint16_t tile_ent, addr;
98
99 tile_ent = vdp_nametab_entry(tile_idx, palidx, VDP_TILE_LOW_PRIO);
100
101 addr = vdp_nametab_addr(nametab_idx) + (y * 64 + x) * 2;
102 vdp_setup_access(addr, VDP_MEM_WRITE, VDP_MEM_VRAM);
103 VDP_PORT_DATA = tile_ent;
104 }
105
106 void vblank_handler(void)
107 {
108 int idx = CYCLE_BEG;
109 uint16_t first;
110
111 first = pal[idx];
112
113 vdp_begin_palette(0, idx);
114 while(idx < CYCLE_END) {
115 pal[idx] = pal[idx + 1];
116 VDP_PORT_DATA = pal[idx];
117 ++idx;
118 }
119 pal[idx] = first;
120 VDP_PORT_DATA = pal[idx];
121 }