1.1 --- a/src/vdp.h	Wed Feb 01 14:40:19 2017 +0200
     1.2 +++ b/src/vdp.h	Sat Feb 11 08:56:42 2017 +0200
     1.3 @@ -10,6 +10,28 @@
     1.4  #define VDP_PORT_HVCOUNT	(*(volatile uint16_t*)0xc00008)
     1.5  #define VDP_PORT_PSG		(*(volatile uint16_t*)0xc00010)
     1.6  
     1.7 +/* registers */
     1.8 +#define VDP_REG_MODE1			0
     1.9 +#define VDP_REG_MODE2			1
    1.10 +#define VDP_REG_PADDR_A			2
    1.11 +#define VDP_REG_PADDR_WIN		3
    1.12 +#define VDP_REG_PADDR_B			4
    1.13 +#define VDP_REG_SPRITE			5
    1.14 +#define VDP_REG_BGCOLOR			7
    1.15 +#define VDP_REG_HINT			10
    1.16 +#define VDP_REG_MODE3			11
    1.17 +#define VDP_REG_MODE4			12
    1.18 +#define VDP_REG_HSCROLL			13
    1.19 +#define VDP_REG_AUTOINC			15
    1.20 +#define VDP_REG_SCROLL_SIZE		16
    1.21 +#define VDP_REG_WINXPOS			17
    1.22 +#define VDP_REG_WINYPOS			18
    1.23 +#define VDP_REG_DMALEN_LOW		19
    1.24 +#define VDP_REG_DMALEN_HIGH		20
    1.25 +#define VDP_REG_DMA_SADDR_LOW	21
    1.26 +#define VDP_REG_DMA_SADDR_MID	22
    1.27 +#define VDP_REG_DMA_SADDR_HIGH	23
    1.28 +
    1.29  /* control register read flags */
    1.30  #define VDP_CTL_PAL_BIT			0x0001
    1.31  #define VDP_CTL_HBLANK_BIT		0x0002
    1.32 @@ -42,12 +64,17 @@
    1.33  #define VDP_REG1_DMA_BIT	0x10
    1.34  #define VDP_REG1_VINTR_BIT	0x20
    1.35  #define VDP_REG1_DISP_BIT	0x40
    1.36 +#define VDP_REG1_XVRAM_BIT	0x80
    1.37  
    1.38  #define VDP_MODE_WR_BIT		1
    1.39  
    1.40  #define VDP_VRAM_WR		1
    1.41  #define VDP_CRAM_WR		3
    1.42  
    1.43 +#define VDP_DMA_MEM_TO_VRAM		0
    1.44 +#define VDP_DMA_VRAM_FILL		2
    1.45 +#define VDP_DMA_VRAM_COPY		3
    1.46 +
    1.47  #define VDP_ADDRSET(addr, mode) /* TODO */
    1.48  
    1.49  #define VDP_CRAM_ADDR32(addr) (0xc0000000 | ((uint32_t)(addr) << 16))
    1.50 @@ -55,15 +82,38 @@
    1.51  #define VDP_SET_CRAM_ADDR(addr) \
    1.52  	do { VDP_PORT_CTL32 = VDP_CRAM_ADDR32(addr); } while(0)
    1.53  
    1.54 +#define VDP_RGB(r, g, b) \
    1.55 +	((((uint16_t)(r) << 1) & 0xe) | \
    1.56 +	 (((uint16_t)(g) << 5) & 0xe0) | \
    1.57 +	 (((uint16_t)(b) << 9) & 0xe00))
    1.58 +
    1.59  #define VDP_RGB24(r, g, b) \
    1.60  	((((uint16_t)(r) >> 4) & 0xe) | \
    1.61  	 ((uint16_t)(g) & 0xe0) | \
    1.62  	 (((uint16_t)(b) << 4) & 0xe00))
    1.63  
    1.64 +#define VDP_SET_CRAM_RGB(r, g, b) \
    1.65 +	do { VDP_PORT_DATA = VDP_RGB(r, g, b); } while(0)
    1.66 +
    1.67  #define VDP_SET_CRAM_RGB24(r, g, b) \
    1.68  	do { VDP_PORT_DATA = VDP_RGB24(r, g, b); } while(0)
    1.69  
    1.70  #define VDP_SET_BGCOLOR(pal, col) \
    1.71 -	do { VDP_SET_REG(7, ((pal) << 4) | (col)); } while(0)
    1.72 +	do { VDP_SET_REG(VDP_REG_BGCOLOR, ((pal) << 4) | (col)); } while(0)
    1.73 +
    1.74 +/* arguments to vdp_tilemap_slot */
    1.75 +#define VDP_PLANE_A		0
    1.76 +#define VDP_PLANE_WIN	1
    1.77 +#define VDP_PLANE_B		2
    1.78 +
    1.79 +int vdp_init(void);
    1.80 +void vdp_set_tilemap_slot(int plane, int slot);
    1.81 +void *vdp_tilemap_ptr(int plane);
    1.82 +void vdp_setpal_rgb24(int idx, int r, int g, int b);
    1.83 +void vdp_setpal(int idx0, int count, unsigned char *pal);
    1.84 +/* TODO vdp_setpal_dma */
    1.85 +
    1.86 +/* xtiles and ytiles can only be 32, 64, or 128 */
    1.87 +void vdp_set_scroll_size(int xtiles, int ytiles);
    1.88  
    1.89  #endif	/* VDP_H_ */