megadrive_test1
diff src/vdp.h @ 7:8253942b0a1a
in the middle of something
author | John Tsiombikas <nuclear@member.fsf.org> |
---|---|
date | Sun, 19 Feb 2017 14:00:26 +0200 |
parents | 862f8a034cae |
children |
line diff
1.1 --- a/src/vdp.h Sat Feb 11 08:56:42 2017 +0200 1.2 +++ b/src/vdp.h Sun Feb 19 14:00:26 2017 +0200 1.3 @@ -11,16 +11,16 @@ 1.4 #define VDP_PORT_PSG (*(volatile uint16_t*)0xc00010) 1.5 1.6 /* registers */ 1.7 -#define VDP_REG_MODE1 0 1.8 -#define VDP_REG_MODE2 1 1.9 +#define VDP_REG_MSET1 0 1.10 +#define VDP_REG_MSET2 1 1.11 #define VDP_REG_PADDR_A 2 1.12 #define VDP_REG_PADDR_WIN 3 1.13 #define VDP_REG_PADDR_B 4 1.14 #define VDP_REG_SPRITE 5 1.15 #define VDP_REG_BGCOLOR 7 1.16 #define VDP_REG_HINT 10 1.17 -#define VDP_REG_MODE3 11 1.18 -#define VDP_REG_MODE4 12 1.19 +#define VDP_REG_MSET3 11 1.20 +#define VDP_REG_MSET4 12 1.21 #define VDP_REG_HSCROLL 13 1.22 #define VDP_REG_AUTOINC 15 1.23 #define VDP_REG_SCROLL_SIZE 16 1.24 @@ -32,6 +32,9 @@ 1.25 #define VDP_REG_DMA_SADDR_MID 22 1.26 #define VDP_REG_DMA_SADDR_HIGH 23 1.27 1.28 +/* shadow copy of any register we set */ 1.29 +unsigned char vdp_shadow_reg[24]; 1.30 + 1.31 /* control register read flags */ 1.32 #define VDP_CTL_PAL_BIT 0x0001 1.33 #define VDP_CTL_HBLANK_BIT 0x0002 1.34 @@ -49,31 +52,33 @@ 1.35 #define VDP_CTL_DATA_MASK 0x00ff 1.36 1.37 #define VDP_RSET(reg, val) \ 1.38 - (0x8000 | (VDP_CTL_REGSEL_MASK & ((uint16_t)(reg) << 8)) | \ 1.39 + (0x8000ul | (VDP_CTL_REGSEL_MASK & ((uint16_t)(reg) << 8)) | \ 1.40 (VDP_CTL_DATA_MASK & (uint16_t)(val))) 1.41 1.42 #define VDP_SET_REG(reg, val) \ 1.43 + do { VDP_PORT_CTL = vdp_shadow_reg[reg] = VDP_RSET(reg, val); } while(0) 1.44 +#define VDP_SET_REG_NOSHADOW(reg, val) \ 1.45 do { VDP_PORT_CTL = VDP_RSET(reg, val); } while(0) 1.46 1.47 -#define VDP_REG0_BASE 4 1.48 -#define VDP_REG0_HVCNT_BIT 0x02 1.49 -#define VDP_REG0_HINTR_BIT 0x10 1.50 +#define VDP_MSET1_BASE 4 1.51 +#define VDP_MSET1_HVCNT_BIT 0x02 1.52 +#define VDP_MSET1_HINTR_BIT 0x10 1.53 1.54 -#define VDP_REG1_BASE 4 1.55 -#define VDP_REG1_30CELL_BIT 0x08 1.56 -#define VDP_REG1_DMA_BIT 0x10 1.57 -#define VDP_REG1_VINTR_BIT 0x20 1.58 -#define VDP_REG1_DISP_BIT 0x40 1.59 -#define VDP_REG1_XVRAM_BIT 0x80 1.60 +#define VDP_MSET2_BASE 4 1.61 +#define VDP_MSET2_30CELL_BIT 0x08 1.62 +#define VDP_MSET2_DMA_BIT 0x10 1.63 +#define VDP_MSET2_VINTR_BIT 0x20 1.64 +#define VDP_MSET2_DISP_BIT 0x40 1.65 +#define VDP_MSET2_XVRAM_BIT 0x80 1.66 1.67 #define VDP_MODE_WR_BIT 1 1.68 1.69 #define VDP_VRAM_WR 1 1.70 #define VDP_CRAM_WR 3 1.71 1.72 -#define VDP_DMA_MEM_TO_VRAM 0 1.73 -#define VDP_DMA_VRAM_FILL 2 1.74 -#define VDP_DMA_VRAM_COPY 3 1.75 +#define VDP_DMA_MEM_VRAM 0 1.76 +#define VDP_DMA_VRAM_FILL 0x80 1.77 +#define VDP_DMA_VRAM_COPY 0xc0 1.78 1.79 #define VDP_ADDRSET(addr, mode) /* TODO */ 1.80 1.81 @@ -101,6 +106,13 @@ 1.82 #define VDP_SET_BGCOLOR(pal, col) \ 1.83 do { VDP_SET_REG(VDP_REG_BGCOLOR, ((pal) << 4) | (col)); } while(0) 1.84 1.85 +#define VDP_TILE_HFLIP (1 << 11) 1.86 +#define VDP_TILE_VFLIP (1 << 12) 1.87 +#define VDP_TILE_PRIO (1 << 15) 1.88 + 1.89 +#define VDP_MKTILE(tidx, pal, flags) \ 1.90 + (((uint16_t)tidx) | ((uint16_t)(pal) << 13) | (flags)) 1.91 + 1.92 /* arguments to vdp_tilemap_slot */ 1.93 #define VDP_PLANE_A 0 1.94 #define VDP_PLANE_WIN 1 1.95 @@ -108,7 +120,7 @@ 1.96 1.97 int vdp_init(void); 1.98 void vdp_set_tilemap_slot(int plane, int slot); 1.99 -void *vdp_tilemap_ptr(int plane); 1.100 +uint32_t vdp_tilemap_addr(int plane); 1.101 void vdp_setpal_rgb24(int idx, int r, int g, int b); 1.102 void vdp_setpal(int idx0, int count, unsigned char *pal); 1.103 /* TODO vdp_setpal_dma */ 1.104 @@ -116,4 +128,6 @@ 1.105 /* xtiles and ytiles can only be 32, 64, or 128 */ 1.106 void vdp_set_scroll_size(int xtiles, int ytiles); 1.107 1.108 +void vdp_memcpy(uint32_t vaddr, void *src, int sz); 1.109 + 1.110 #endif /* VDP_H_ */