1.1 --- a/src/main.c	Sat Feb 11 08:56:42 2017 +0200
     1.2 +++ b/src/main.c	Sun Feb 19 14:00:26 2017 +0200
     1.3 @@ -17,7 +17,7 @@
     1.4  
     1.5  int main(void)
     1.6  {
     1.7 -	unsigned char *tmap;
     1.8 +	uint16_t *tmap;
     1.9  
    1.10  	vdp_init();
    1.11  
    1.12 @@ -28,5 +28,6 @@
    1.13  	tmap = vdp_tilemap_ptr(VDP_PLANE_A);
    1.14  
    1.15  
    1.16 +
    1.17  	return 0;
    1.18  }

     2.1 --- a/src/startup.s	Sat Feb 11 08:56:42 2017 +0200
     2.2 +++ b/src/startup.s	Sun Feb 19 14:00:26 2017 +0200
     2.3 @@ -4,6 +4,9 @@
     2.4  	.global start
     2.5  	.global halt_cpu
     2.6  start:
     2.7 +	| copy the string 'SEGA' to appease the TMSS
     2.8 +	move.l 100, 0xa14000 | SEGA is always at address 100
     2.9 +
    2.10  	| copy .data section from ROM to RAM
    2.11  	move.l #_data_lma, %a0
    2.12  	move.l #_data_start, %a1
    2.13 @@ -24,6 +27,10 @@
    2.14  	cmp.l %a0, %a1
    2.15  	bne.s 0b
    2.16  1:
    2.17 +
    2.18 +	| setup the stack pointer stack
    2.19 +	move.l #_stacktop, %sp
    2.20 +
    2.21  	jsr main
    2.22  halt_cpu:
    2.23  	stop #0x2700

     3.1 --- a/src/vdp.c	Sat Feb 11 08:56:42 2017 +0200
     3.2 +++ b/src/vdp.c	Sun Feb 19 14:00:26 2017 +0200
     3.3 @@ -3,18 +3,20 @@
     3.4  #include "io.h"
     3.5  #include "misc.h"
     3.6  
     3.7 -static void *tilemap_ptr[3];
     3.8 +unsigned char vdp_shadow_reg[24];
     3.9 +
    3.10 +static uint32_t tilemap_addr[3];
    3.11  
    3.12  int vdp_init(void)
    3.13  {
    3.14 -	unsigned int mode1_flags = VDP_REG1_DISP_BIT;
    3.15 +	unsigned int mode1_flags = VDP_MSET2_DISP_BIT;
    3.16  
    3.17  	if(mdg_ispal()) {
    3.18 -		mode1_flags |= VDP_REG1_30CELL_BIT;
    3.19 +		mode1_flags |= VDP_MSET2_30CELL_BIT;
    3.20  	}
    3.21  
    3.22 -	VDP_SET_REG(0, VDP_REG0_BASE);
    3.23 -	VDP_SET_REG(1, VDP_REG1_BASE | mode1_flags);
    3.24 +	VDP_SET_REG(VDP_REG_MSET1, VDP_MSET1_BASE);
    3.25 +	VDP_SET_REG(VDP_REG_MSET2, VDP_MSET2_BASE | mode1_flags);
    3.26  
    3.27  	return 0;
    3.28  }
    3.29 @@ -24,24 +26,24 @@
    3.30  	switch(plane) {
    3.31  	case VDP_PLANE_A:
    3.32  		VDP_SET_REG(VDP_REG_PADDR_A, (slot & 7) << 3);
    3.33 -		tilemap_ptr[VDP_PLANE_A] = (void*)((uint32_t)slot << 13);
    3.34 +		tilemap_addr[VDP_PLANE_A] = ((uint32_t)slot << 13);
    3.35  		break;
    3.36  
    3.37  	case VDP_PLANE_WIN:
    3.38  		VDP_SET_REG(VDP_REG_PADDR_WIN, (slot & 0x1f) << 1);
    3.39 -		tilemap_ptr[VDP_PLANE_WIN] = (void*)((uint32_t)slot << 11);
    3.40 +		tilemap_addr[VDP_PLANE_WIN] = ((uint32_t)slot << 11);
    3.41  		break;
    3.42  
    3.43  	case VDP_PLANE_B:
    3.44  		VDP_SET_REG(VDP_REG_PADDR_B, slot & 7);
    3.45 -		tilemap_ptr[VDP_PLANE_B] = (void*)((uint32_t)slot << 13);
    3.46 +		tilemap_addr[VDP_PLANE_B] = ((uint32_t)slot << 13);
    3.47  		break;
    3.48  	}
    3.49  }
    3.50  
    3.51 -void *vdp_tilemap_ptr(int plane)
    3.52 +uint32_t vdp_tilemap_addr(int plane)
    3.53  {
    3.54 -	return tilemap_ptr[plane];
    3.55 +	return tilemap_addr[plane];
    3.56  }
    3.57  
    3.58  void vdp_setpal_rgb24(int idx, int r, int g, int b)
    3.59 @@ -83,3 +85,19 @@
    3.60  
    3.61  	VDP_SET_REG(VDP_REG_SCROLL_SIZE, (ytiles << 4) | xtiles);
    3.62  }
    3.63 +
    3.64 +void vdp_memcpy(uint32_t vaddr, void *src, int sz)
    3.65 +{
    3.66 +	uint32_t saddr = (uint32_t)src;
    3.67 +	sz >>= 1;	/* we'll transfer words */
    3.68 +	VDP_SET_REG_NOSHADOW(VDP_REG_MSET2,
    3.69 +			vdp_shadow_reg[VDP_REG_MSET2] | VDP_MSET2_DMA_BIT);
    3.70 +	VDP_SET_REG(VDP_REG_AUTOINC, 2);
    3.71 +	VDP_SET_REG(VDP_REG_DMALEN_LOW, sz);
    3.72 +	VDP_SET_REG(VDP_REG_DMALEN_HIGH, sz >> 8);
    3.73 +	VDP_SET_REG(VDP_REG_DMA_SADDR_LOW, saddr >> 1);
    3.74 +	VDP_SET_REG(VDP_REG_DMA_SADDR_MID, saddr >> 9);
    3.75 +	VDP_SET_REG(VDP_REG_DMA_SADDR_HIGH, saddr >> 17);
    3.76 +
    3.77 +	VDP_PORT_CTL = (vaddr & 0x3ffe) | 
    3.78 +}

     4.1 --- a/src/vdp.h	Sat Feb 11 08:56:42 2017 +0200
     4.2 +++ b/src/vdp.h	Sun Feb 19 14:00:26 2017 +0200
     4.3 @@ -11,16 +11,16 @@
     4.4  #define VDP_PORT_PSG		(*(volatile uint16_t*)0xc00010)
     4.5  
     4.6  /* registers */
     4.7 -#define VDP_REG_MODE1			0
     4.8 -#define VDP_REG_MODE2			1
     4.9 +#define VDP_REG_MSET1			0
    4.10 +#define VDP_REG_MSET2			1
    4.11  #define VDP_REG_PADDR_A			2
    4.12  #define VDP_REG_PADDR_WIN		3
    4.13  #define VDP_REG_PADDR_B			4
    4.14  #define VDP_REG_SPRITE			5
    4.15  #define VDP_REG_BGCOLOR			7
    4.16  #define VDP_REG_HINT			10
    4.17 -#define VDP_REG_MODE3			11
    4.18 -#define VDP_REG_MODE4			12
    4.19 +#define VDP_REG_MSET3			11
    4.20 +#define VDP_REG_MSET4			12
    4.21  #define VDP_REG_HSCROLL			13
    4.22  #define VDP_REG_AUTOINC			15
    4.23  #define VDP_REG_SCROLL_SIZE		16
    4.24 @@ -32,6 +32,9 @@
    4.25  #define VDP_REG_DMA_SADDR_MID	22
    4.26  #define VDP_REG_DMA_SADDR_HIGH	23
    4.27  
    4.28 +/* shadow copy of any register we set */
    4.29 +unsigned char vdp_shadow_reg[24];
    4.30 +
    4.31  /* control register read flags */
    4.32  #define VDP_CTL_PAL_BIT			0x0001
    4.33  #define VDP_CTL_HBLANK_BIT		0x0002
    4.34 @@ -49,31 +52,33 @@
    4.35  #define VDP_CTL_DATA_MASK		0x00ff
    4.36  
    4.37  #define VDP_RSET(reg, val)	\
    4.38 -	(0x8000 | (VDP_CTL_REGSEL_MASK & ((uint16_t)(reg) << 8)) | \
    4.39 +	(0x8000ul | (VDP_CTL_REGSEL_MASK & ((uint16_t)(reg) << 8)) | \
    4.40  	 (VDP_CTL_DATA_MASK & (uint16_t)(val)))
    4.41  
    4.42  #define VDP_SET_REG(reg, val) \
    4.43 +	do { VDP_PORT_CTL = vdp_shadow_reg[reg] = VDP_RSET(reg, val); } while(0)
    4.44 +#define VDP_SET_REG_NOSHADOW(reg, val) \
    4.45  	do { VDP_PORT_CTL = VDP_RSET(reg, val); } while(0)
    4.46  
    4.47 -#define VDP_REG0_BASE		4
    4.48 -#define VDP_REG0_HVCNT_BIT	0x02
    4.49 -#define VDP_REG0_HINTR_BIT	0x10
    4.50 +#define VDP_MSET1_BASE		4
    4.51 +#define VDP_MSET1_HVCNT_BIT	0x02
    4.52 +#define VDP_MSET1_HINTR_BIT	0x10
    4.53  
    4.54 -#define VDP_REG1_BASE		4
    4.55 -#define VDP_REG1_30CELL_BIT	0x08
    4.56 -#define VDP_REG1_DMA_BIT	0x10
    4.57 -#define VDP_REG1_VINTR_BIT	0x20
    4.58 -#define VDP_REG1_DISP_BIT	0x40
    4.59 -#define VDP_REG1_XVRAM_BIT	0x80
    4.60 +#define VDP_MSET2_BASE		4
    4.61 +#define VDP_MSET2_30CELL_BIT	0x08
    4.62 +#define VDP_MSET2_DMA_BIT	0x10
    4.63 +#define VDP_MSET2_VINTR_BIT	0x20
    4.64 +#define VDP_MSET2_DISP_BIT	0x40
    4.65 +#define VDP_MSET2_XVRAM_BIT	0x80
    4.66  
    4.67  #define VDP_MODE_WR_BIT		1
    4.68  
    4.69  #define VDP_VRAM_WR		1
    4.70  #define VDP_CRAM_WR		3
    4.71  
    4.72 -#define VDP_DMA_MEM_TO_VRAM		0
    4.73 -#define VDP_DMA_VRAM_FILL		2
    4.74 -#define VDP_DMA_VRAM_COPY		3
    4.75 +#define VDP_DMA_MEM_VRAM		0
    4.76 +#define VDP_DMA_VRAM_FILL		0x80
    4.77 +#define VDP_DMA_VRAM_COPY		0xc0
    4.78  
    4.79  #define VDP_ADDRSET(addr, mode) /* TODO */
    4.80  
    4.81 @@ -101,6 +106,13 @@
    4.82  #define VDP_SET_BGCOLOR(pal, col) \
    4.83  	do { VDP_SET_REG(VDP_REG_BGCOLOR, ((pal) << 4) | (col)); } while(0)
    4.84  
    4.85 +#define VDP_TILE_HFLIP	(1 << 11)
    4.86 +#define VDP_TILE_VFLIP	(1 << 12)
    4.87 +#define VDP_TILE_PRIO	(1 << 15)
    4.88 +
    4.89 +#define VDP_MKTILE(tidx, pal, flags)	\
    4.90 +	(((uint16_t)tidx) | ((uint16_t)(pal) << 13) | (flags))
    4.91 +
    4.92  /* arguments to vdp_tilemap_slot */
    4.93  #define VDP_PLANE_A		0
    4.94  #define VDP_PLANE_WIN	1
    4.95 @@ -108,7 +120,7 @@
    4.96  
    4.97  int vdp_init(void);
    4.98  void vdp_set_tilemap_slot(int plane, int slot);
    4.99 -void *vdp_tilemap_ptr(int plane);
   4.100 +uint32_t vdp_tilemap_addr(int plane);
   4.101  void vdp_setpal_rgb24(int idx, int r, int g, int b);
   4.102  void vdp_setpal(int idx0, int count, unsigned char *pal);
   4.103  /* TODO vdp_setpal_dma */
   4.104 @@ -116,4 +128,6 @@
   4.105  /* xtiles and ytiles can only be 32, 64, or 128 */
   4.106  void vdp_set_scroll_size(int xtiles, int ytiles);
   4.107  
   4.108 +void vdp_memcpy(uint32_t vaddr, void *src, int sz);
   4.109 +
   4.110  #endif	/* VDP_H_ */