gb_test2
view test.asm @ 3:d7c6e1165028
added input handling
author | John Tsiombikas <nuclear@member.fsf.org> |
---|---|
date | Thu, 10 Jan 2019 06:05:21 +0200 |
parents | a8b7297e7e2c |
children | 216bdbc75cf4 |
line source
1 ; vi:ft=rgbasm:
2 include "hw.inc"
4 xoffs_center equ 4
5 yoffs_center equ 12
7 frame equ $ff80
8 bnstate equ $ff81
9 bnxor equ $ff82
10 pause equ $ff83
12 BN_A equ $01
13 BN_B equ $02
14 BN_SELECT equ $04
15 BN_START equ $08
16 BN_RIGHT equ $10
17 BN_LEFT equ $20
18 BN_UP equ $40
19 BN_DOWN equ $80
21 section "hdr", ROM0[$100]
22 nop
23 jp main
25 rept $150 - $104
26 db 0
27 endr
29 section "text", ROM0
31 main:
32 call init
34 xor a, a
35 ldh [frame], a
36 ldh [bnstate], a
37 ldh [bnxor], a
38 ldh [pause], a
40 .mainloop:
41 ldh a, [REG_LY]
42 cp a, 144
43 jr c, .wait_hsync
45 ; we're in vsync, increment frame counter, handle input,
46 ; and wait for the next frame
47 call read_input
49 ; swap palette if A is pressed
50 ldh a, [bnxor]
51 and a, BN_A
52 jr z, .skip_akey ; skip if A haven't changed state since last frame
53 ldh a, [bnstate]
54 and a, BN_A
55 jr z, .skip_akey ; skip if A is not pressed
56 ldh a, [REG_BGP]
57 cpl
58 ldh [REG_BGP], a
59 .skip_akey:
60 ; toggle pause if start is pressed
61 ldh a, [bnxor]
62 and a, BN_START
63 jr z, .skip_startkey ; skip if start haven't changed state since last frame
64 ldh a, [bnstate]
65 and a, BN_START
66 jr z, .skip_startkey ; skip if start is not pressed
67 ldh a, [pause]
68 cpl
69 ldh [pause], a
70 .skip_startkey:
72 ; increment frame if we're not paused
73 ldh a, [pause]
74 bit 0, a
75 jr nz, .skip_frameinc
76 ldh a, [frame]
77 inc a
78 ldh [frame], a
79 .skip_frameinc:
82 .wait_newframe:
83 ldh a, [REG_LY]
84 cp a, 0
85 jr nz, .wait_newframe
87 ; scanline code
88 .wait_hsync:
89 ldh a, [REG_STAT]
90 and a, STAT_MODE_MASK
91 jr nz, .wait_hsync
93 ldh a, [frame]
94 ld d, a
96 xor a, a
97 ld b, a
99 ldh a, [REG_LY]
100 add a, d ; add frame number
101 ld c, a
103 ld hl, sintab
104 add hl, bc ; hl now points to the sine value
106 ld a, [hl]
108 ; add a half-octave sine
109 ld e, a ; save first sine to e
110 sla d
111 ld a, [REG_LY]
112 sla a
113 add a, d
114 ld c, a
115 srl d
117 ld hl, sintab
118 add hl, bc
119 ld a, [hl]
120 sra a
121 add a, e ; add previously saved sine
123 add a, yoffs_center
124 ldh [REG_SCY], a
126 ; do something for SCX too
127 ld a, d
128 sla a
129 ld d, a
131 ldh a, [REG_LY]
132 add a, 32
133 add a, d ; add frame number
134 ld c, a
136 ld hl, sintab
137 add hl, bc
139 ld a, [hl]
140 sra a
141 add a, xoffs_center
142 ldh [REG_SCX], a
144 ; done, wait until we're out of hsync
145 .wait_endhsync:
146 ldh a, [REG_STAT]
147 and a, STAT_MODE_MASK
148 jr z, .wait_endhsync
150 jp .mainloop
153 di
154 .end: halt
155 nop
156 jp .end
158 init:
159 call wait_vsync
160 xor a, a
161 ldh [REG_LCDC], a
163 ; setup palette
164 ld a, $1b
165 ldh [REG_BGP], a
167 ; copy tiles
168 ld hl, $8000
169 ld de, tiles
170 ld bc, tiles_end - tiles
171 .copytiles:
172 ld a, [de]
173 ld [hl+], a
174 inc de
175 dec bc
176 ld a, b
177 or c
178 jp nz, .copytiles
180 ; copy tilemap
181 ld hl, $9800
182 ld de, tilemap
183 ld b, 21
184 .copymap:
185 ld c, 21
186 .copymaprow:
187 ld a, [de]
188 inc de
189 ld [hl+], a
190 dec c
191 jr nz, .copymaprow
193 push bc
194 ld bc, 11
195 add hl, bc
196 pop bc
198 dec b
199 jr nz, .copymap
201 ; center viewport
202 ld a, yoffs_center
203 ldh [REG_SCY], a
204 ld a, xoffs_center
205 ldh [REG_SCX], a
207 ; configure LCD
208 ld a, LCDC_DISPON | LCDC_CHAR_8000 | LCDC_BGON
209 ldh [REG_LCDC], a
210 ret
212 wait_vsync:
213 ldh a, [REG_LY]
214 cp a, 144
215 jr c, wait_vsync
216 ret
218 read_input:
219 ; read D-pad
220 ld a, P1_DPAD
221 ld [REG_P1], a
222 ld a, [REG_P1]
223 ld a, [REG_P1]
224 cpl
225 and a, $0f
226 swap a
227 ld b, a
228 ; read buttons
229 ld a, P1_BUTTONS
230 ld [REG_P1], a
231 ld a, [REG_P1]
232 ld a, [REG_P1]
233 ld a, [REG_P1]
234 ld a, [REG_P1]
235 ld a, [REG_P1]
236 ld a, [REG_P1]
237 cpl
238 and a, $0f
239 or a, b
240 ld b, a
241 ; reset port
242 ld a, P1_DPAD | P1_BUTTONS
243 ldh [REG_P1], a
244 ; calculate differences and save state variables
245 ldh a, [bnstate]
246 xor a, b
247 ldh [bnxor], a
248 ld a, b
249 ldh [bnstate], a
250 ret
252 section "data", ROM0, align[8]
253 sintab:
254 include "sin.inc"
256 tiles:
257 incbin "logo.tiles"
258 tiles_end:
259 tilemap:
260 incbin "logo.tilemap"
261 tilemap_end: