1.1 --- a/src/dsregs.h	Mon Jan 29 03:48:05 2018 +0200
     1.2 +++ b/src/dsregs.h	Mon Jan 29 14:40:45 2018 +0200
     1.3 @@ -211,17 +211,31 @@
     1.4  #define REG_VRAMCNT_I	REG8(0x249)
     1.5  
     1.6  /* ---- math hardware registers ---- */
     1.7 -#define REG_DIVCNT		REG16(0x280)
     1.8 -#define REG_DIV_NUMER	REG64(0x290)
     1.9 -#define REG_DIV_DENOM	REG64(0x298)
    1.10 -#define REG_DIV_RESULT	REG64(0x2a0)
    1.11 +#define REG_DIVCNT			REG32(0x280)
    1.12 +#define REG_DIV_NUMER		REG64(0x290)
    1.13 +#define REG_DIV_NUMERL		REG32(0x290)
    1.14 +#define REG_DIV_NUMERH		REG32(0x294)
    1.15 +#define REG_DIV_DENOM		REG64(0x298)
    1.16 +#define REG_DIV_DENOML		REG32(0x298)
    1.17 +#define REG_DIV_DENOMH		REG32(0x29c)
    1.18 +#define REG_DIV_RESULT		REG64(0x2a0)
    1.19 +#define REG_DIV_RESULTL		REG32(0x2a0)
    1.20 +#define REG_DIV_RESULTH		REG32(0x2a4)
    1.21  #define REG_DIVREM_RESULT	REG64(0x2a8)
    1.22 -#define REG_SQRTCNT		REG16(0x2b0)
    1.23 -#define REG_SQRT_RESULT	REG32(0x2b4)
    1.24 -#define REG_SQRT_PARAM	REG64(0x2b8)
    1.25 -#define REG_POSTFLG		REG32(0x300)
    1.26 -#define REG_POWCNT1		REG16(0x304)
    1.27 -#define REG_POWCNT2		REG16(0x304)
    1.28 +#define REG_DIVREM_RESULTL	REG32(0x2a8)
    1.29 +#define REG_DIVREM_RESULTH	REG32(0x2ac)
    1.30 +#define REG_SQRTCNT			REG16(0x2b0)
    1.31 +#define REG_SQRT_RESULT		REG32(0x2b4)
    1.32 +#define REG_SQRT_PARAM		REG64(0x2b8)
    1.33 +#define REG_POSTFLG			REG32(0x300)
    1.34 +#define REG_POWCNT1			REG16(0x304)
    1.35 +#define REG_POWCNT2			REG16(0x304)
    1.36 +
    1.37 +#define DIVCNT_32_32		0
    1.38 +#define DIVCNT_64_32		1
    1.39 +#define DIVCNT_64_64		2
    1.40 +#define DIVCNT_DIV0			0x4000
    1.41 +#define DIVCNT_BUSY			0x8000
    1.42  
    1.43  #define POWCNT1_LCD			0x0001
    1.44  #define POWCNT1_2DA			0x0002