nds_test1
changeset 0:ab2afb70001a tip
initial commit test1 without libnds
| author | John Tsiombikas <nuclear@member.fsf.org> |
|---|---|
| date | Sat, 27 Jan 2018 23:38:00 +0200 |
| parents | |
| children | |
| files | .hgignore Makefile data/icon.bmp.base64 src/arm7/main.c src/dsregs.h src/main.c src/startup/arm7entry.s src/startup/arm9entry.s src/startup/mpu_setup.S |
| diffstat | 9 files changed, 1091 insertions(+), 0 deletions(-) [+] |
line diff
1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 1.2 +++ b/.hgignore Sat Jan 27 23:38:00 2018 +0200 1.3 @@ -0,0 +1,7 @@ 1.4 +\.o$ 1.5 +\.d$ 1.6 +\.swp$ 1.7 +\.elf$ 1.8 +\.bin$ 1.9 +\.nds$ 1.10 +\.bmp$
2.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 2.2 +++ b/Makefile Sat Jan 27 23:38:00 2018 +0200 2.3 @@ -0,0 +1,45 @@ 2.4 +csrc = $(wildcard src/*.c) 2.5 +ssrc = src/startup/arm9entry.s $(wildcard src/*.s) 2.6 +Ssrc = $(wildcard src/startup/*.S) $(wildcard src/*.S) 2.7 +obj = $(csrc:.c=.o) $(ssrc:.s=.o) $(Ssrc:.S=.o) 2.8 + 2.9 +csrc-arm7 = $(wildcard src/arm7/*.c) 2.10 +ssrc-arm7 = src/startup/arm7entry.s $(wildcard src/arm7/*.s) 2.11 +obj-arm7 = $(csrc-arm7:.c=.o) $(ssrc-arm7:.s=.o) 2.12 + 2.13 +name = test1 2.14 +bin = $(name).nds 2.15 + 2.16 +ARCH = arm-none-eabi- 2.17 +CPP = $(ARCH)cpp 2.18 +CC = $(ARCH)gcc 2.19 +AS = $(ARCH)as 2.20 +OBJCOPY = $(ARCH)objcopy 2.21 + 2.22 +EMU = desmume-cli 2.23 + 2.24 +opt = -fomit-frame-pointer -mcpu=arm946e-s -mtune=arm946e-s 2.25 +dbg = -g 2.26 + 2.27 +CFLAGS = -mthumb $(opt) $(dbg) 2.28 +LDFLAGS = -nostartfiles -Wl,--gc-sections -lm 2.29 + 2.30 +$(bin): arm9.elf arm7.elf data/icon.bmp 2.31 + ndstool -c $@ -9 arm9.elf -7 arm7.elf -b data/icon.bmp "$(name);mindlapse" 2.32 + 2.33 +arm9.elf: $(obj) 2.34 + $(CC) -o $@ $(obj) -Wl,-T,ds_arm9.mem -Wl,-T,ds_arm9.ld $(LDFLAGS) 2.35 + 2.36 +arm7.elf: $(obj-arm7) 2.37 + $(CC) -o $@ $(obj-arm7) -Wl,-T,ds_arm7.ld $(LDFLAGS) 2.38 + 2.39 +.PHONY: clean 2.40 +clean: 2.41 + rm -f $(obj) $(obj-arm7) $(bin) arm9.elf arm7.elf $(dep) 2.42 + 2.43 +.PHONY: simrun 2.44 +simrun: $(bin) 2.45 + $(EMU) $(EMUFLAGS) $(bin) 2.46 + 2.47 +data/icon.bmp: data/icon.bmp.base64 2.48 + base64 -d $< >$@
3.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 3.2 +++ b/data/icon.bmp.base64 Sat Jan 27 23:38:00 2018 +0200 3.3 @@ -0,0 +1,37 @@ 3.4 +Qk02CAAAAAAAADYEAAAoAAAAIAAAACAAAAABAAgAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAb29h 3.5 +AFBHQgBgW1IAen9pAIWNbgCOk30Al6R7AKGmjACjt3cArraTAL3AoQA3KCgARDQ2AMa9twAfExYA 3.6 +2c/NAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBv 3.7 +b2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9v 3.8 +YQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29h 3.9 +AG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EA 3.10 +b29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBv 3.11 +b2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9v 3.12 +YQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29h 3.13 +AG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EA 3.14 +b29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBv 3.15 +b2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9v 3.16 +YQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29h 3.17 +AG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EA 3.18 +b29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBv 3.19 +b2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9v 3.20 +YQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29h 3.21 +AG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EA 3.22 +b29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAG9vYQBvb2EAb29hAA4ODg4O 3.23 +Dg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4O 3.24 +Dg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4O 3.25 +Dg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4O 3.26 +Dg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODgsLDg4ODg4ODg4ODg4ODg4O 3.27 +Dg4ODg4ODg4ODg4ODg4LDgsODg4ODg4ODg4ODg4ODg4ODg4ODgsLDg4ODgsODg4ODg4ODg4ODg4O 3.28 +AgADAwAAAg4ODgEDDQAODgIDBQMDAgIAAAUFBAwODg4FBwMEBwYHAAQFBwoPAg4LAQcDAwQHAgUD 3.29 +BAMLDg4OCwUFDg4LAgcABAIHBQcCDg4OCw4OAAcBCw4ODg4ODgsMBQULCw4OAAQOAAcLBwMHBQUE 3.30 +BQcHAAsFBwAODg4ODAEFBQEMDg4CBwMHAA4GAgAACQkAAQ4ODAELDg4ODg4BAgcNAAELDgMPCQQO 3.31 +CwUFAwMHCgUDAwAFAAAABQEODgECDQ8CDAsOAg0JAgAFBQUFAwAABAUEBQgFAwMCDg4ODAIPBwsB 3.32 +Ag4CBwAOBwcOAgcADg4ODgIECAkFAQ4ODg4LAQcEDgMFDgIHDg4EBA4BBQAODg4BBQQABQcJAg4O 3.33 +Dg4LBQUOAwcOAgcODgUEDgEDAg4OAQMFAQ4MAQUHAQ4ODg4FBQAFCQMCBw4OBAUOAQMCDgwFBQEL 3.34 +CwsBAQUADg4ODgUFBwcHCgQFCw4EBw4BBAMBAwMCDAwBAQsFBQEODg4OAwkFAgIHCgULDgcDDgEE 3.35 +CQkFAgsCAQICAwUADg4ODg4FBwAODgIHBQEOBgUMAQQGAwELAgQHBQUFAg4ODg4ODgQCDg4ODgEA 3.36 +DA4DAgsABQIMDgIHBwQAAAELDg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODgsMAQIBDAsODg4ODg4O 3.37 +Dg4ODg4ODg4ODg4ODg4ODg4ODgsMDAsLDg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4O 3.38 +Dg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4O 3.39 +Dg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4O 3.40 +Dg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4ODg4=
4.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 4.2 +++ b/src/arm7/main.c Sat Jan 27 23:38:00 2018 +0200 4.3 @@ -0,0 +1,4 @@ 4.4 +int main(void) 4.5 +{ 4.6 + for(;;); 4.7 +}
5.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 5.2 +++ b/src/dsregs.h Sat Jan 27 23:38:00 2018 +0200 5.3 @@ -0,0 +1,360 @@ 5.4 +#ifndef DSREGS_H_ 5.5 +#define DSREGS_H_ 5.6 + 5.7 +#include <stdint.h> 5.8 + 5.9 +#define REG_BASE 0x4000000 5.10 +#define REG8(x) (*(volatile int8_t*)(REG_BASE + (x))) 5.11 +#define REG16(x) (*(volatile int16_t*)(REG_BASE + (x))) 5.12 +#define REG32(x) (*(volatile int32_t*)(REG_BASE + (x))) 5.13 +#define REG64(x) (*(volatile int64_t*)(REG_BASE + (x))) 5.14 + 5.15 +/* ---- display engine A ---- */ 5.16 +#define REG_DISPCNT REG32(0x00) 5.17 +#define REG_DISPSTAT REG16(0x04) 5.18 +#define REG_VCOUNT REG16(0x06) 5.19 +#define REG_BG0CNT REG16(0x08) 5.20 +#define REG_BG1CNT REG16(0x0a) 5.21 +#define REG_BG2CNT REG16(0x0c) 5.22 +#define REG_BG3CNT REG16(0x0e) 5.23 +/* scrolling registers */ 5.24 +#define REG_BG0HOFS REG16(0x10) 5.25 +#define REG_BG0VOFS REG16(0x12) 5.26 +#define REG_BG1HOFS REG16(0x14) 5.27 +#define REG_BG1VOFS REG16(0x16) 5.28 +#define REG_BG2HOFS REG16(0x18) 5.29 +#define REG_BG2VOFS REG16(0x1a) 5.30 +#define REG_BG3HOFS REG16(0x1c) 5.31 +#define REG_BG3VOFS REG16(0x1e) 5.32 +/* BG rotation and scaling registers */ 5.33 +#define REG_BG2PA REG16(0x20) 5.34 +#define REG_BG2PB REG16(0x22) 5.35 +#define REG_BG2PC REG16(0x24) 5.36 +#define REG_BG2PD REG16(0x26) 5.37 +#define REG_BG2X REG32(0x28) 5.38 +#define REG_BG2Y REG32(0x2c) 5.39 +#define REG_BG3PA REG16(0x30) 5.40 +#define REG_BG3PB REG16(0x32) 5.41 +#define REG_BG3PC REG16(0x34) 5.42 +#define REG_BG3PD REG16(0x36) 5.43 +#define REG_BG3X REG32(0x38) 5.44 +#define REG_BG3Y REG32(0x3c) 5.45 +/* window registers */ 5.46 +#define REG_WIN0H REG16(0x40) 5.47 +#define REG_WIN1H REG16(0x42) 5.48 +#define REG_WIN0V REG16(0x44) 5.49 +#define REG_WIN1V REG16(0x46) 5.50 +#define REG_WININ REG16(0x48) 5.51 +#define REG_WINOUT REG16(0x4a) 5.52 +/* mosaic */ 5.53 +#define REG_MOSAIC REG16(0x4c) 5.54 +/* color effects */ 5.55 +#define REG_BLDCNT REG16(0x50) 5.56 +#define REG_BLDALPHA REG16(0x52) 5.57 +#define REG_BLDY REG16(0x54) 5.58 + 5.59 +#define REG_DISP3DCNT REG16(0x60) 5.60 +#define REG_DISPCAPCNT REG32(0x64) 5.61 +#define REG_DISP_MMEM_FIFO REG32(0x68) 5.62 +#define REG_MASTER_BRIGHT REG16(0x6c) 5.63 + 5.64 +/* ---- display engine B ---- */ 5.65 +#define REG_B_DISPCNT REG32(0x1000) 5.66 +#define REG_B_BG0CNT REG16(0x1008) 5.67 +#define REG_B_BG1CNT REG16(0x100a) 5.68 +#define REG_B_BG2CNT REG16(0x100c) 5.69 +#define REG_B_BG3CNT REG16(0x100e) 5.70 +/* scrolling registers */ 5.71 +#define REG_B_BG0HOFS REG16(0x1010) 5.72 +#define REG_B_BG0VOFS REG16(0x1012) 5.73 +#define REG_B_BG1HOFS REG16(0x1014) 5.74 +#define REG_B_BG1VOFS REG16(0x1016) 5.75 +#define REG_B_BG2HOFS REG16(0x1018) 5.76 +#define REG_B_BG2VOFS REG16(0x101a) 5.77 +#define REG_B_BG3HOFS REG16(0x101c) 5.78 +#define REG_B_BG3VOFS REG16(0x101e) 5.79 +/* BG rotation and scaling registers */ 5.80 +#define REG_B_BG2PA REG16(0x1020) 5.81 +#define REG_B_BG2PB REG16(0x1022) 5.82 +#define REG_B_BG2PC REG16(0x1024) 5.83 +#define REG_B_BG2PD REG16(0x1026) 5.84 +#define REG_B_BG2X REG32(0x1028) 5.85 +#define REG_B_BG2Y REG32(0x102c) 5.86 +#define REG_B_BG3PA REG16(0x1030) 5.87 +#define REG_B_BG3PB REG16(0x1032) 5.88 +#define REG_B_BG3PC REG16(0x1034) 5.89 +#define REG_B_BG3PD REG16(0x1036) 5.90 +#define REG_B_BG3X REG32(0x1038) 5.91 +#define REG_B_BG3Y REG32(0x103c) 5.92 +/* window registers */ 5.93 +#define REG_B_WIN0H REG16(0x1040) 5.94 +#define REG_B_WIN1H REG16(0x1042) 5.95 +#define REG_B_WIN0V REG16(0x1044) 5.96 +#define REG_B_WIN1V REG16(0x1046) 5.97 +#define REG_B_WININ REG16(0x1048) 5.98 +#define REG_B_WINOUT REG16(0x104a) 5.99 +/* mosaic */ 5.100 +#define REG_B_MOSAIC REG16(0x104c) 5.101 +/* color effects */ 5.102 +#define REG_B_BLDCNT REG16(0x1050) 5.103 +#define REG_B_BLDALPHA REG16(0x1052) 5.104 +#define REG_B_BLDY REG16(0x1054) 5.105 + 5.106 +#define REG_B_MASTER_BRIGHT REG16(0x106c) 5.107 + 5.108 + 5.109 +#define DISPCNT_BGMODE(x) (x) 5.110 +#define DISPCNT_MODE(x) ((uint32_t)(x) << 16) 5.111 +#define DISPCNT_BG0_3D 0x00000008 5.112 +#define DISPCNT_TILE_OBJ_1DMAP 0x00000010 5.113 +#define DISPCNT_BM_OBJ_256X256 0x00000020 5.114 +#define DISPCNT_BM_OBJ_1DMAP 0x00000040 5.115 +#define DISPCNT_BLANK 0x00000080 5.116 +#define DISPCNT_BG0 0x00000100 5.117 +#define DISPCNT_BG1 0x00000200 5.118 +#define DISPCNT_BG2 0x00000400 5.119 +#define DISPCNT_BG3 0x00000800 5.120 +#define DISPCNT_OBJ 0x00001000 5.121 +#define DISPCNT_WIN0 0x00002000 5.122 +#define DISPCNT_WIN1 0x00004000 5.123 +#define DISPCNT_OBJWIN 0x00008000 5.124 + 5.125 +#define BGXCNT_PRIO(x) (x) 5.126 +#define BGXCNT_CHARBASE(x) ((x) << 2) 5.127 +#define BGXCNT_MOSAIC 0x0040 5.128 +#define BGXCNT_COL_256 0x0080 5.129 +#define BGXCNT_BM 0x0080 5.130 +#define BGXCNT_SCRBASE(x) ((x) << 8) 5.131 +#define BGXCNT_OVF_WRAP 0x2000 5.132 +#define BGXCNT_SCRSIZE(x) ((x) << 14) 5.133 +#define BGXCNT_TX_256X256 BGXCNT_SCRSIZE(0) 5.134 +#define BGXCNT_TX_512X256 BGXCNT_SCRSIZE(1) 5.135 +#define BGXCNT_TX_256X512 BGXCNT_SCRSIZE(2) 5.136 +#define BGXCNT_TX_512X512 BGXCNT_SCRSIZE(3) 5.137 +#define BGXCNT_RS_128X128 BGXCNT_SCRSIZE(0) 5.138 +#define BGXCNT_RS_256X256 BGXCNT_SCRSIZE(1) 5.139 +#define BGXCNT_RS_512X512 BGXCNT_SCRSIZE(2) 5.140 +#define BGXCNT_RS_1024X1024 BGXCNT_SCRSIZE(3) 5.141 +#define BGXCNT_BM_128X128 (BGXCNT_SCRSIZE(0) | BGXCNT_BM) 5.142 +#define BGXCNT_BM_256X256 (BGXCNT_SCRSIZE(1) | BGXCNT_BM) 5.143 +#define BGXCNT_BM_512X256 (BGXCNT_SCRSIZE(2) | BGXCNT_BM) 5.144 +#define BGXCNT_BM_512X512 (BGXCNT_SCRSIZE(3) | BGXCNT_BM) 5.145 +#define BGXCNT_BM8 0 5.146 +#define BGXCNT_BM16 0x0004 5.147 + 5.148 +#define VRAM_OFFSET(x) ((x) << 3) 5.149 +#define VRAM_ENABLE 0x80 5.150 + 5.151 +/* ---- DMA registers ---- */ 5.152 +#define REG_DMA0SAD REG32(0xb0) 5.153 +#define REG_DMA0DAD REG32(0xb4) 5.154 +#define REG_DMA0CNT_L REG16(0xb8) 5.155 +#define REG_DMA0CNT_H REG16(0xba) 5.156 +#define REG_DMA1SAD REG32(0xbc) 5.157 +#define REG_DMA1DAD REG32(0xc0) 5.158 +#define REG_DMA1CNT_L REG16(0xc4) 5.159 +#define REG_DMA1CNT_H REG16(0xc6) 5.160 +#define REG_DMA2SAD REG32(0xc8) 5.161 +#define REG_DMA2DAD REG32(0xcc) 5.162 +#define REG_DMA2CNT_L REG16(0xd0) 5.163 +#define REG_DMA2CNT_H REG16(0xd2) 5.164 +#define REG_DMA3SAD REG32(0xd4) 5.165 +#define REG_DMA3DAD REG32(0xd8) 5.166 +#define REG_DMA3CNT_L REG16(0xdc) 5.167 +#define REG_DMA3CNT_H REG16(0xde) 5.168 +#define REG_DMA0FILL REG32(0xe0) 5.169 +#define REG_DMA1FILL REG32(0xe4) 5.170 +#define REG_DMA2FILL REG32(0xe8) 5.171 +#define REG_DMA3FILL REG32(0xec) 5.172 + 5.173 +/* ---- timer registers ---- */ 5.174 +#define REG_TM0CNT_L REG16(0x100) 5.175 +#define REG_TM0CNT_H REG16(0x102) 5.176 +#define REG_TM1CNT_L REG16(0x104) 5.177 +#define REG_TM1CNT_H REG16(0x106) 5.178 +#define REG_TM2CNT_L REG16(0x108) 5.179 +#define REG_TM2CNT_H REG16(0x10a) 5.180 +#define REG_TM3CNT_L REG16(0x10c) 5.181 +#define REG_TM3CNT_H REG16(0x10e) 5.182 + 5.183 +/* ---- keypad registers ---- */ 5.184 +#define REG_KEYINPUT REG16(0x130) 5.185 +#define REG_KEYCNT REG16(0x132) 5.186 + 5.187 +/* ---- IPC/ROM registers ---- */ 5.188 +#define REG_IPCSYNC REG16(0x180) 5.189 +#define REG_IPCFIFOCNT REG16(0x184) 5.190 +#define REG_IPCFIFOSEND REG32(0x188) 5.191 +#define REG_AUXSPICNT REG16(0x1a0) 5.192 +#define REG_AUXSPIDATA REG16(0x1a2) 5.193 +#define REG_GCARDCNT REG32(0x1a4) 5.194 +#define REG_GCARDCMD64 REG64(0x1a8) 5.195 +#define REG_GCARDSEED0 REG32(0x1b0) 5.196 +#define REG_GCARDSEED1 REG32(0x1b4) 5.197 +#define REG_GCARDSEED0X REG16(0x1b8) 5.198 +#define REG_GCARDSEED1X REG16(0x1ba) 5.199 + 5.200 +/* ---- memory & IRQ control registers ---- */ 5.201 +#define REG_EXMEMCNT REG16(0x204) 5.202 +#define REG_IME REG16(0x208) 5.203 +#define REG_IE REG32(0x210) 5.204 +#define REG_IF REG32(0x214) 5.205 +#define REG_VRAMCNT_A REG8(0x240) 5.206 +#define REG_VRAMCNT_B REG8(0x241) 5.207 +#define REG_VRAMCNT_C REG8(0x242) 5.208 +#define REG_VRAMCNT_D REG8(0x243) 5.209 +#define REG_VRAMCNT_E REG8(0x244) 5.210 +#define REG_VRAMCNT_F REG8(0x245) 5.211 +#define REG_VRAMCNT_G REG8(0x246) 5.212 +#define REG_WRAMCNT REG8(0x247) 5.213 +#define REG_VRAMCNT_H REG8(0x248) 5.214 +#define REG_VRAMCNT_I REG8(0x249) 5.215 + 5.216 +/* ---- math hardware registers ---- */ 5.217 +#define REG_DIVCNT REG16(0x280) 5.218 +#define REG_DIV_NUMER REG64(0x290) 5.219 +#define REG_DIV_DENOM REG64(0x298) 5.220 +#define REG_DIV_RESULT REG64(0x2a0) 5.221 +#define REG_DIVREM_RESULT REG64(0x2a8) 5.222 +#define REG_SQRTCNT REG16(0x2b0) 5.223 +#define REG_SQRT_RESULT REG32(0x2b4) 5.224 +#define REG_SQRT_PARAM REG64(0x2b8) 5.225 +#define REG_POSTFLG REG32(0x300) 5.226 +#define REG_POWCNT1 REG16(0x304) 5.227 +#define REG_POWCNT2 REG16(0x304) 5.228 + 5.229 +#define POWCNT1_LCD 0x0001 5.230 +#define POWCNT1_2DA 0x0002 5.231 +#define POWCNT1_3DREND 0x0004 5.232 +#define POWCNT1_3DGEOM 0x0008 5.233 +#define POWCNT1_2DB 0x0200 5.234 +#define POWCNT1_DSWAP 0x8000 5.235 + 5.236 +#define POWCNT2_SOUND 0x0001 5.237 +#define POWCNT2_WIFI 0x0002 5.238 + 5.239 +/* ---- sound registers ---- */ 5.240 +#define REG_SOUNDXCNT(x) REG32(0x400 | ((x) << 4)) 5.241 +#define REG_SOUNDXSAD(x) REG32(0x404 | ((x) << 4)) 5.242 +#define REG_SOUNDXTMR(x) REG32(0x408 | ((x) << 4)) 5.243 +#define REG_SOUNDXPNT(x) REG32(0x40a | ((x) << 4)) 5.244 +#define REG_SOUNDXLEN(x) REG32(0x40c | ((x) << 4)) 5.245 +#define REG_SOUNDCNT REG32(0x500) 5.246 +#define REG_SOUNDBIAS REG32(0x504) 5.247 + 5.248 +/* ---- 3D hardware registers ---- */ 5.249 +/* rendering engine */ 5.250 +#define REG_RDLINES_COUNR REG8(0x320) 5.251 +#define REG_EDGE_COLOR0 REG16(0x330) 5.252 +#define REG_EDGE_COLOR1 REG16(0x332) 5.253 +#define REG_EDGE_COLOR2 REG16(0x334) 5.254 +#define REG_EDGE_COLOR3 REG16(0x336) 5.255 +#define REG_EDGE_COLOR4 REG16(0x338) 5.256 +#define REG_EDGE_COLOR5 REG16(0x33a) 5.257 +#define REG_EDGE_COLOR6 REG16(0x33c) 5.258 +#define REG_EDGE_COLOR7 REG16(0x33e) 5.259 +#define REG_ALPHA_TEST_REF REG8(0x340) 5.260 +#define REG_CLEAR_COLOR REG32(0x350) 5.261 +#define REG_CLEAR_DEPTH REG16(0x354) 5.262 +#define REG_CLRIMAGE_OFFSET REG16(0x356) 5.263 +#define REG_FOG_COLOR REG32(0x358) 5.264 +#define REG_FOG_OFFSET REG16(0x35c) 5.265 +#define FOG_TABLE_ADDR ((uint8_t*)(REG_BASE + 0x360)) 5.266 +#define TOON_TABLE_ADDR ((uint16_t*)(REG_BASE + 0x380)) 5.267 +/* geometry engine */ 5.268 +#define GXFIFO_ADDR ((uint8_t*)(REG_BASE + 0x400)) 5.269 +#define REG_GXSTAT REG32(0x600) 5.270 +#define REG_RAM_COUNT REG32(0x604) 5.271 +#define REG_DISP_1DOT_DEPTH REG16(0x610) 5.272 +#define POS_RESULT_ADDR ((uint8_t*)(REG_BASE + 0x620)) 5.273 +#define VEC_RESULT_ADDR ((uint8_t*)(REG_BASE + 0x630)) 5.274 +#define CLIPMTX_RESULT_ADDR ((uint32_t*)(REG_BASE + 0x640)) 5.275 +#define VECMTX_RESULT_ADDR ((uint32_t*)(REG_BASE + 0x680)) 5.276 +/* geometry command ports */ 5.277 +#define REG_MTX_MODE REG32(0x440) /* 1 */ 5.278 +#define REG_MTX_PUSH REG32(0x444) /* 0 */ 5.279 +#define REG_MTX_POP REG32(0x448) /* 1 */ 5.280 +#define REG_MTX_STORE REG32(0x44c) /* 1 */ 5.281 +#define REG_MTX_RESTORE REG32(0x450) /* 1 */ 5.282 +#define REG_MTX_IDENTITY REG32(0x454) /* 0 */ 5.283 +#define REG_MTX_LOAD_4X4 REG32(0x458) /* 16 */ 5.284 +#define REG_MTX_LOAD_4X3 REG32(0x45c) /* 12 */ 5.285 +#define REG_MTX_MULT_4X4 REG32(0x460) /* 16 */ 5.286 +#define REG_MTX_MULT_4X3 REG32(0x464) /* 12 */ 5.287 +#define REG_MTX_MULT_3X3 REG32(0x468) /* 9 */ 5.288 +#define REG_MTX_SCALE REG32(0x46c) /* 3 */ 5.289 +#define REG_MTX_TRANS REG32(0x470) /* 3 */ 5.290 +#define REG_COLOR REG32(0x480) /* 1 */ 5.291 +#define REG_NORMAL REG32(0x484) /* 1 */ 5.292 +#define REG_TEXCOORD REG32(0x488) /* 1 */ 5.293 +#define REG_VTX_16 REG32(0x48c) /* 2 */ 5.294 +#define REG_VTX_10 REG32(0x490) /* 1 */ 5.295 +#define REG_VTX_XY REG32(0x494) /* 1 */ 5.296 +#define REG_VTX_XZ REG32(0x498) /* 1 */ 5.297 +#define REG_VTX_YZ REG32(0x49c) /* 1 */ 5.298 +#define REG_VTX_DIFF REG32(0x4a0) /* 1 */ 5.299 +#define REG_POLYGON_ATTR REG32(0x4a4) /* 1 */ 5.300 +#define REG_TEXIMAGE_PARAM REG32(0x4a8) /* 1 */ 5.301 +#define REG_PLTT_BASE REG32(0x4ac) /* 1 */ 5.302 +#define REG_DIF_AMB REG32(0x4c0) /* 1 */ 5.303 +#define REG_SPE_EMI REG32(0x4c4) /* 1 */ 5.304 +#define REG_LIGHT_VECTOR REG32(0x4c8) /* 1 */ 5.305 +#define REG_LIGHT_COLOR REG32(0x4cc) /* 1 */ 5.306 +#define REG_SHININESS REG32(0x4d0) /* 32 */ 5.307 +#define REG_BEGIN_VTXS REG32(0x500) /* 1 */ 5.308 +#define REG_END_VTXS REG32(0x504) /* 0 */ 5.309 +#define REG_SWAP_BUFFERS REG32(0x540) /* 1 */ 5.310 +#define REG_VIEWPORT REG32(0x580) /* 1 */ 5.311 +#define REG_BOX_TEST REG32(0x5c0) /* 3 */ 5.312 +#define REG_POS_TEST REG32(0x5c4) /* 2 */ 5.313 +#define REG_VEC_TEST REG32(0x5c8) /* 1 */ 5.314 + 5.315 +/* geometry commands */ 5.316 +#define GCMD_MTX_MODE 0x10 /* 1 */ 5.317 +#define GCMD_MTX_PUSH 0x11 /* 0 */ 5.318 +#define GCMD_MTX_POP 0x12 /* 1 */ 5.319 +#define GCMD_MTX_STORE 0x13 /* 1 */ 5.320 +#define GCMD_MTX_RESTORE 0x14 /* 1 */ 5.321 +#define GCMD_MTX_IDENTITY 0x15 /* 0 */ 5.322 +#define GCMD_MTX_LOAD_4X4 0x16 /* 16 */ 5.323 +#define GCMD_MTX_LOAD_4X3 0x17 /* 12 */ 5.324 +#define GCMD_MTX_MULT_4X4 0x18 /* 16 */ 5.325 +#define GCMD_MTX_MULT_4X3 0x19 /* 12 */ 5.326 +#define GCMD_MTX_MULT_3X3 0x1a /* 9 */ 5.327 +#define GCMD_MTX_SCALE 0x1b /* 3 */ 5.328 +#define GCMD_MTX_TRANS 0x1c /* 3 */ 5.329 +#define GCMD_COLOR 0x20 /* 1 */ 5.330 +#define GCMD_NORMAL 0x21 /* 1 */ 5.331 +#define GCMD_TEXCOORD 0x22 /* 1 */ 5.332 +#define GCMD_VTX_16 0x23 /* 2 */ 5.333 +#define GCMD_VTX_10 0x24 /* 1 */ 5.334 +#define GCMD_VTX_XY 0x25 /* 1 */ 5.335 +#define GCMD_VTX_XZ 0x26 /* 1 */ 5.336 +#define GCMD_VTX_YZ 0x27 /* 1 */ 5.337 +#define GCMD_VTX_DIFF 0x28 /* 1 */ 5.338 +#define GCMD_POLYGON_ATTR 0x29 /* 1 */ 5.339 +#define GCMD_TEXIMAGE_PARAM 0x2a /* 1 */ 5.340 +#define GCMD_PLTT_BASE 0x2b /* 1 */ 5.341 +#define GCMD_DIF_AMB 0x30 /* 1 */ 5.342 +#define GCMD_SPE_EMI 0x31 /* 1 */ 5.343 +#define GCMD_LIGHT_VECTOR 0x32 /* 1 */ 5.344 +#define GCMD_LIGHT_COLOR 0x33 /* 1 */ 5.345 +#define GCMD_SHININESS 0x34 /* 32 */ 5.346 +#define GCMD_BEGIN_VTXS 0x40 /* 1 */ 5.347 +#define GCMD_END_VTXS 0x41 /* 0 */ 5.348 +#define GCMD_SWAP_BUFFERS 0x50 /* 1 */ 5.349 +#define GCMD_VIEWPORT 0x60 /* 1 */ 5.350 +#define GCMD_BOX_TEST 0x70 /* 3 */ 5.351 +#define GCMD_POS_TEST 0x71 /* 2 */ 5.352 +#define GCMD_VEC_TEST 0x72 /* 1 */ 5.353 + 5.354 +/* addresses of interest */ 5.355 +#define SHARED_WRAM_PTR ((void*)0x3000000) 5.356 +#define VRAM_BGA_PTR ((void*)0x6000000) 5.357 +#define VRAM_BGB_PTR ((void*)0x6200000) 5.358 +#define VRAM_OBJA_PTR ((void*)0x6400000) 5.359 +#define VRAM_OBJB_PTR ((void*)0x6600000) 5.360 +#define VRAM_LCDC_PTR ((void*)0x6800000) 5.361 +#define OAM_PTR ((void*)0x7000000) 5.362 + 5.363 +#endif /* DSREGS_H_ */
6.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 6.2 +++ b/src/main.c Sat Jan 27 23:38:00 2018 +0200 6.3 @@ -0,0 +1,68 @@ 6.4 +#include <stdint.h> 6.5 +#include <math.h> 6.6 +#include "dsregs.h" 6.7 + 6.8 +static void xorpat(void *addr, int xsz, int ysz); 6.9 + 6.10 +static void *vram = VRAM_LCDC_PTR; 6.11 +static uint16_t *bgmem = VRAM_BGB_PTR; 6.12 + 6.13 +int main(void) 6.14 +{ 6.15 + uint32_t frame; 6.16 + 6.17 + REG_POWCNT1 = POWCNT1_LCD | POWCNT1_2DA | POWCNT1_2DB | POWCNT1_DSWAP; 6.18 + 6.19 + REG_DISPCNT = DISPCNT_MODE(2); 6.20 + REG_B_DISPCNT = DISPCNT_MODE(1) | DISPCNT_BG2 | 5; 6.21 + 6.22 + REG_B_BG2CNT = BGXCNT_BM_256X256 | BGXCNT_BM16 | BGXCNT_OVF_WRAP; 6.23 + REG_B_BG2PA = 0x100; 6.24 + REG_B_BG2PB = 0; 6.25 + REG_B_BG2PC = 0; 6.26 + REG_B_BG2PD = 0x100; 6.27 + 6.28 + REG_VRAMCNT_A = VRAM_ENABLE; 6.29 + REG_VRAMCNT_C = VRAM_ENABLE | 4; 6.30 + 6.31 + xorpat(vram, 256, 192); 6.32 + xorpat(bgmem, 256, 256); 6.33 + 6.34 + for(;;) { 6.35 + float t = (float)frame * 0.00035; 6.36 + float scale = 0.5 * sin(t * 0.8) + 0.8; 6.37 + int32_t sa = (int16_t)(sin(t) * 256 * scale); 6.38 + int32_t ca = (int16_t)(cos(t) * 256 * scale); 6.39 + 6.40 + int32_t x = ca * -128 + sa * -96 + (128 << 8); 6.41 + int32_t y = -sa * -128 + ca * -96 + (96 << 8); 6.42 + 6.43 + while(REG_VCOUNT < 192); 6.44 + 6.45 + REG_B_BG2PA = ca; 6.46 + REG_B_BG2PB = sa; 6.47 + REG_B_BG2PC = -sa; 6.48 + REG_B_BG2PD = ca; 6.49 + REG_B_BG2X = x; 6.50 + REG_B_BG2Y = y; 6.51 + 6.52 + ++frame; 6.53 + } 6.54 + return 0; 6.55 +} 6.56 + 6.57 +static void xorpat(void *addr, int xsz, int ysz) 6.58 +{ 6.59 + int i, j; 6.60 + uint16_t *p = addr; 6.61 + 6.62 + for(i=0; i<ysz; i++) { 6.63 + for(j=0; j<xsz; j++) { 6.64 + int xor = i^j; 6.65 + uint16_t red = xor >> 2; 6.66 + uint16_t green = xor >> 1; 6.67 + uint16_t blue = xor; 6.68 + *p++ = 0x8000 | red | ((green & 0x1f) << 5) | ((blue & 0x1f) << 10); 6.69 + } 6.70 + } 6.71 +}
7.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 7.2 +++ b/src/startup/arm7entry.s Sat Jan 27 23:38:00 2018 +0200 7.3 @@ -0,0 +1,175 @@ 7.4 +@ vi:set filetype=armasm: 7.5 + .section ".crt0","ax" 7.6 + .global _start 7.7 + .align 4 7.8 + .arm 7.9 +_start: 7.10 + mov r0, #0x04000000 @ IME = 0; 7.11 + mov r1, #0 7.12 + str r1, [r0, #0x208] 7.13 + 7.14 + mov r0, #0x12 @ Switch to IRQ Mode 7.15 + msr cpsr, r0 7.16 + ldr sp, =__sp_irq @ Set IRQ stack 7.17 + 7.18 + mov r0, #0x13 @ Switch to SVC Mode 7.19 + msr cpsr, r0 7.20 + ldr sp, =__sp_svc @ Set SVC stack 7.21 + 7.22 + mov r0, #0x1F @ Switch to System Mode 7.23 + msr cpsr, r0 7.24 + ldr sp, =__sp_usr @ Set user stack 7.25 + 7.26 +#ifndef VRAM 7.27 + adr r1, __sync_start @ Perform ARM7<->ARM9 sync code 7.28 + ldr r2, =__arm7_start__ 7.29 + mov r3, #(__sync_end-__sync_start) 7.30 + mov r8, r2 7.31 + bl CopyMem 7.32 + mov r3, r8 7.33 + bl _blx_r3_stub 7.34 + 7.35 +@ Copy arm7 binary from LMA to VMA (EWRAM to IWRAM) 7.36 + adr r0, arm7lma @ Calculate ARM7 LMA 7.37 + ldr r1, [r0] 7.38 + add r1, r1, r0 7.39 + ldr r2, =__arm7_start__ 7.40 + ldr r4, =__arm7_end__ 7.41 + bl CopyMemCheck 7.42 + 7.43 +#else 7.44 + bl __sync_start 7.45 +#endif 7.46 + 7.47 + ldr r0, =__bss_start__ @ Clear BSS section to 0x00 7.48 + ldr r1, =__bss_end__ 7.49 + sub r1, r1, r0 7.50 + bl ClearMem 7.51 + 7.52 +#ifndef VRAM 7.53 + cmp r10, #1 7.54 + bne NotTWL 7.55 + ldr r1, =__dsimode @ set DSi mode flag 7.56 + strb r10, [r1] 7.57 + 7.58 + ldr r1, =0x02ffe1d8 @ Get ARM7i LMA from header 7.59 + ldr r1, [r1] 7.60 + ldr r2, =__arm7i_start__ 7.61 + ldr r4, =__arm7i_end__ 7.62 + bl CopyMemCheck 7.63 + 7.64 + ldr r0, =__twl_bss_start__ @ Clear TWL BSS section to 0x00 7.65 + ldr r1, =__twl_bss_end__ 7.66 + sub r1, r1, r0 7.67 + bl ClearMem 7.68 +#endif 7.69 + 7.70 +NotTWL: 7.71 + mov r0, #0 @ int argc 7.72 + mov r1, #0 @ char *argv[] 7.73 + ldr r3, =main 7.74 + mov r12, #0x4000000 @ tell arm9 we are ready 7.75 + mov r9, #0 7.76 + str r9, [r12, #0x180] 7.77 +_blx_r3_stub: 7.78 + bx r3 7.79 +infloop: 7.80 + b infloop 7.81 + 7.82 +#ifndef VRAM 7.83 +arm7lma: 7.84 + .word __arm7_lma__ - . 7.85 +#endif 7.86 + .pool 7.87 + 7.88 +@--------------------------------------------------------------------------------- 7.89 +@ ARM7<->ARM9 synchronization code 7.90 +@--------------------------------------------------------------------------------- 7.91 + 7.92 +__sync_start: 7.93 + push {lr} 7.94 + mov r12, #0x4000000 7.95 + mov r9, #0x0 7.96 + bl IPCSync 7.97 + mov r9, #(0x9<<8) 7.98 + str r9, [r12, #0x180] 7.99 + mov r9, #0xA 7.100 + bl IPCSync 7.101 + mov r9, #(0xB<<8) 7.102 + str r9, [r12, #0x180] 7.103 + mov r9, #0xC 7.104 + bl IPCSync 7.105 + mov r9, #(0xD<<8) 7.106 + str r9, [r12, #0x180] 7.107 +IPCRecvFlag: 7.108 + ldr r10, [r12, #0x180] 7.109 + and r10, r10, #0xF 7.110 + cmp r10, #0xC 7.111 + beq IPCRecvFlag 7.112 + pop {pc} 7.113 +IPCSync: 7.114 + ldr r10, [r12, #0x180] 7.115 + and r10, r10, #0xF 7.116 + cmp r10, r9 7.117 + bne IPCSync 7.118 + bx lr 7.119 +__sync_end: 7.120 + 7.121 +@--------------------------------------------------------------------------------- 7.122 +@ Clear memory to 0x00 if length != 0 7.123 +@ r0 = Start Address 7.124 +@ r1 = Length 7.125 +@--------------------------------------------------------------------------------- 7.126 +ClearMem: 7.127 +@--------------------------------------------------------------------------------- 7.128 + mov r2, #3 @ Round down to nearest word boundary 7.129 + add r1, r1, r2 @ Shouldn't be needed 7.130 + bics r1, r1, r2 @ Clear 2 LSB (and set Z) 7.131 + bxeq lr @ Quit if copy size is 0 7.132 + 7.133 + mov r2, #0 7.134 +ClrLoop: 7.135 + stmia r0!, {r2} 7.136 + subs r1, r1, #4 7.137 + bne ClrLoop 7.138 + bx lr 7.139 + 7.140 +@--------------------------------------------------------------------------------- 7.141 +@ Copy memory if length != 0 7.142 +@ r1 = Source Address 7.143 +@ r2 = Dest Address 7.144 +@ r4 = Dest Address + Length 7.145 +@--------------------------------------------------------------------------------- 7.146 +CopyMemCheck: 7.147 +@--------------------------------------------------------------------------------- 7.148 + cmp r1, r2 7.149 + bxeq lr 7.150 + 7.151 + sub r3, r4, r2 @ Is there any data to copy? 7.152 +@--------------------------------------------------------------------------------- 7.153 +@ Copy memory 7.154 +@ r1 = Source Address 7.155 +@ r2 = Dest Address 7.156 +@ r3 = Length 7.157 +@--------------------------------------------------------------------------------- 7.158 +CopyMem: 7.159 +@--------------------------------------------------------------------------------- 7.160 + mov r0, #3 @ These commands are used in cases where 7.161 + add r3, r3, r0 @ the length is not a multiple of 4, 7.162 + bics r3, r3, r0 @ even though it should be. 7.163 + bxeq lr @ Length is zero, so exit 7.164 +CIDLoop: 7.165 + ldmia r1!, {r0} 7.166 + stmia r2!, {r0} 7.167 + subs r3, r3, #4 7.168 + bne CIDLoop 7.169 + bx lr 7.170 + 7.171 +@--------------------------------------------------------------------------------- 7.172 + .align 7.173 + .pool 7.174 + 7.175 + .global __dsimode 7.176 +__dsimode: .word 7.177 + .end 7.178 +@---------------------------------------------------------------------------------
8.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 8.2 +++ b/src/startup/arm9entry.s Sat Jan 27 23:38:00 2018 +0200 8.3 @@ -0,0 +1,192 @@ 8.4 +@ vi:set filetype=armasm: 8.5 + .arch armv5te 8.6 + .cpu arm946e-s 8.7 + .section ".crt0","ax" 8.8 + .global _start 8.9 + .align 4 8.10 + .arm 8.11 +_start: 8.12 + mov r0, #0x04000000 @ IME = 0; 8.13 + str r0, [r0, #0x208] 8.14 + 8.15 + @ set sensible stacks to allow bios call 8.16 + 8.17 + mov r0, #0x13 @ Switch to SVC Mode 8.18 + msr cpsr, r0 8.19 + mov r1,#0x03000000 8.20 + sub r1,r1,#0x1000 8.21 + mov sp,r1 8.22 + mov r0, #0x1F @ Switch to System Mode 8.23 + msr cpsr, r0 8.24 + sub r1,r1,#0x100 8.25 + mov sp,r1 8.26 + 8.27 + ldr r3, =mpu_setup 8.28 + blx r3 8.29 + 8.30 + mov r0, #0x12 @ Switch to IRQ Mode 8.31 + msr cpsr, r0 8.32 + ldr sp, =__sp_irq @ Set IRQ stack 8.33 + 8.34 + mov r0, #0x13 @ Switch to SVC Mode 8.35 + msr cpsr, r0 8.36 + ldr sp, =__sp_svc @ Set SVC stack 8.37 + 8.38 + mov r0, #0x1F @ Switch to System Mode 8.39 + msr cpsr, r0 8.40 + ldr sp, =__sp_usr @ Set user stack 8.41 + 8.42 + mov r12, #0x4000000 @ Read system ROM status (NTR/TWL) 8.43 + ldrb r11, [r12,r12,lsr #12] 8.44 + and r11, r11, #0x3 8.45 + 8.46 + b skip_sync 8.47 + 8.48 + mov r9, #(0x0<<8) @ Synchronize with ARM7 8.49 + str r9, [r12, #0x180] 8.50 + mov r9, #0x9 8.51 + bl IPCSync 8.52 + mov r9, #(0xA<<8) 8.53 + str r9, [r12, #0x180] 8.54 + mov r9, #0xB 8.55 + bl IPCSync 8.56 + mov r9, #(0xC<<8) 8.57 + str r9, [r12, #0x180] 8.58 + mov r9, #0xD 8.59 + bl IPCSync 8.60 + mov r9, r11, lsl #8 8.61 + str r9, [r12, #0x180] 8.62 + mov r9, #0 8.63 + bl IPCSync 8.64 + str r9, [r12, #0x180] 8.65 + 8.66 +skip_sync: 8.67 + 8.68 + ldr r1, =__itcm_lma @ Copy instruction tightly coupled memory (itcm section) from LMA to VMA 8.69 + ldr r2, =__itcm_start 8.70 + ldr r4, =__itcm_end 8.71 + bl CopyMemCheck 8.72 + 8.73 + ldr r1, =__vectors_lma @ Copy reserved vectors area (itcm section) from LMA to VMA 8.74 + ldr r2, =__vectors_start 8.75 + ldr r4, =__vectors_end 8.76 + bl CopyMemCheck 8.77 + 8.78 + ldr r1, =__dtcm_lma @ Copy data tightly coupled memory (dtcm section) from LMA to VMA 8.79 + ldr r2, =__dtcm_start 8.80 + ldr r4, =__dtcm_end 8.81 + bl CopyMemCheck 8.82 + 8.83 + cmp r11, #1 8.84 + ldrne r10, =__end__ @ (DS mode) heap start 8.85 + ldreq r10, =__twl_end__ @ (DSi mode) heap start 8.86 + 8.87 + ldr r0, =__bss_start__ @ Clear BSS section 8.88 + ldr r1, =__bss_end__ 8.89 + sub r1, r1, r0 8.90 + bl ClearMem 8.91 + 8.92 + ldr r0, =__sbss_start @ Clear SBSS section 8.93 + ldr r1, =__sbss_end 8.94 + sub r1, r1, r0 8.95 + bl ClearMem 8.96 + 8.97 + cmp r11, #1 8.98 + bne NotTWL 8.99 + ldr r9, =__dsimode @ set DSi mode flag 8.100 + strb r11, [r9] 8.101 + 8.102 + @ Copy TWL area (arm9i section) from LMA to VMA 8.103 + ldr r1, =0x02ffe1c8 @ Get ARM9i LMA from header 8.104 + ldr r1, [r1] 8.105 + 8.106 + ldr r2, =__arm9i_start__ 8.107 + cmp r1, r2 @ skip copy if LMA=VMA 8.108 + ldrne r4, =__arm9i_end__ 8.109 + blne CopyMemCheck 8.110 + 8.111 + ldr r0, =__twl_bss_start__ @ Clear TWL BSS section 8.112 + ldr r1, =__twl_bss_end__ 8.113 + sub r1, r1, r0 8.114 + bl ClearMem 8.115 + 8.116 +NotTWL: 8.117 + ldr r0, =__secure_area__ 8.118 + ldr r3, =main 8.119 + bx r3 @ jump to user code 8.120 +infloop: 8.121 + b infloop 8.122 + 8.123 + 8.124 + 8.125 +@--------------------------------------------------------------------------------- 8.126 +@ Clear memory to 0x00 if length != 0 8.127 +@ r0 = Start Address 8.128 +@ r1 = Length 8.129 +@--------------------------------------------------------------------------------- 8.130 +ClearMem: 8.131 +@--------------------------------------------------------------------------------- 8.132 + mov r2, #3 @ Round down to nearest word boundary 8.133 + add r1, r1, r2 @ Shouldn't be needed 8.134 + bics r1, r1, r2 @ Clear 2 LSB (and set Z) 8.135 + bxeq lr @ Quit if copy size is 0 8.136 + 8.137 + mov r2, #0 8.138 +ClrLoop: 8.139 + stmia r0!, {r2} 8.140 + subs r1, r1, #4 8.141 + bne ClrLoop 8.142 + 8.143 + bx lr 8.144 + 8.145 +@--------------------------------------------------------------------------------- 8.146 +@ Copy memory if length != 0 8.147 +@ r1 = Source Address 8.148 +@ r2 = Dest Address 8.149 +@ r4 = Dest Address + Length 8.150 +@--------------------------------------------------------------------------------- 8.151 +CopyMemCheck: 8.152 +@--------------------------------------------------------------------------------- 8.153 + sub r3, r4, r2 @ Is there any data to copy? 8.154 +@--------------------------------------------------------------------------------- 8.155 +@ Copy memory 8.156 +@ r1 = Source Address 8.157 +@ r2 = Dest Address 8.158 +@ r3 = Length 8.159 +@--------------------------------------------------------------------------------- 8.160 +CopyMem: 8.161 +@--------------------------------------------------------------------------------- 8.162 + mov r0, #3 @ These commands are used in cases where 8.163 + add r3, r3, r0 @ the length is not a multiple of 4, 8.164 + bics r3, r3, r0 @ even though it should be. 8.165 + bxeq lr @ Length is zero, so exit 8.166 +CIDLoop: 8.167 + ldmia r1!, {r0} 8.168 + stmia r2!, {r0} 8.169 + subs r3, r3, #4 8.170 + bne CIDLoop 8.171 + 8.172 + bx lr 8.173 + 8.174 +@ Synchronize with ARM7 8.175 +IPCSync: 8.176 + ldr r10, [r12, #0x180] 8.177 + and r10, r10, #0xF 8.178 + cmp r10, r9 8.179 + bne IPCSync 8.180 + bx lr 8.181 + 8.182 + 8.183 + .align 8.184 + .pool 8.185 + 8.186 + .data 8.187 + .global __dsimode 8.188 +__dsimode: 8.189 + .word 0 8.190 + 8.191 + .section ".secure","a" 8.192 + .align 2 8.193 + .global __secure_area__ 8.194 +__secure_area__: 8.195 + .space 2048, 0
9.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 9.2 +++ b/src/startup/mpu_setup.S Sat Jan 27 23:38:00 2018 +0200 9.3 @@ -0,0 +1,203 @@ 9.4 +@ vi:set filetype=armasm: 9.5 +#define PAGE_4K (0b01011 << 1) 9.6 +#define PAGE_8K (0b01100 << 1) 9.7 +#define PAGE_16K (0b01101 << 1) 9.8 +#define PAGE_32K (0b01110 << 1) 9.9 +#define PAGE_64K (0b01111 << 1) 9.10 +#define PAGE_128K (0b10000 << 1) 9.11 +#define PAGE_256K (0b10001 << 1) 9.12 +#define PAGE_512K (0b10010 << 1) 9.13 +#define PAGE_1M (0b10011 << 1) 9.14 +#define PAGE_2M (0b10100 << 1) 9.15 +#define PAGE_4M (0b10101 << 1) 9.16 +#define PAGE_8M (0b10110 << 1) 9.17 +#define PAGE_16M (0b10111 << 1) 9.18 +#define PAGE_32M (0b11000 << 1) 9.19 +#define PAGE_64M (0b11001 << 1) 9.20 +#define PAGE_128M (0b11010 << 1) 9.21 +#define PAGE_256M (0b11011 << 1) 9.22 +#define PAGE_512M (0b11100 << 1) 9.23 +#define PAGE_1G (0b11101 << 1) 9.24 +#define PAGE_2G (0b11110 << 1) 9.25 +#define PAGE_4G (0b11111 << 1) 9.26 + 9.27 +#define ITCM_LOAD (1<<19) 9.28 +#define ITCM_ENABLE (1<<18) 9.29 +#define DTCM_LOAD (1<<17) 9.30 +#define DTCM_ENABLE (1<<16) 9.31 +#define DISABLE_TBIT (1<<15) 9.32 +#define ROUND_ROBIN (1<<14) 9.33 +#define ALT_VECTORS (1<<13) 9.34 +#define ICACHE_ENABLE (1<<12) 9.35 +#define BIG_ENDIAN (1<<7) 9.36 +#define DCACHE_ENABLE (1<<2) 9.37 +#define PROTECT_ENABLE (1<<0) 9.38 + 9.39 + .arch armv5te 9.40 + .cpu arm946e-s 9.41 + 9.42 + .text 9.43 + .arm 9.44 + 9.45 + .global mpu_setup 9.46 + .align 2 9.47 +mpu_setup: 9.48 +@ turn the power on for M3 9.49 + ldr r1, =0x8203 9.50 + mov r0, #0x04000000 9.51 + add r0, r0, #0x304 9.52 + strh r1, [r0] 9.53 + 9.54 + ldr r1, =0x00002078 @ disable TCM and protection unit 9.55 + mcr p15, 0, r1, c1, c0 9.56 + 9.57 +@ Protection Unit Setup added by Sasq 9.58 + @ Disable cache 9.59 + mov r0, #0 9.60 + mcr p15, 0, r0, c7, c5, 0 @ Instruction cache 9.61 + mcr p15, 0, r0, c7, c6, 0 @ Data cache 9.62 + 9.63 + @ Wait for write buffer to empty 9.64 + mcr p15, 0, r0, c7, c10, 4 9.65 + 9.66 + ldr r0, =__dtcm_start 9.67 + orr r0,r0,#0x0a 9.68 + mcr p15, 0, r0, c9, c1,0 @ DTCM base = __dtcm_start, size = 16 KB 9.69 + 9.70 + mov r0,#0x20 9.71 + mcr p15, 0, r0, c9, c1,1 @ ITCM base = 0 , size = 32 MB 9.72 + 9.73 +@ Setup memory regions similar to Release Version 9.74 + @ Region 0 - IO registers 9.75 + ldr r0,=( PAGE_64M | 0x04000000 | 1) 9.76 + mcr p15, 0, r0, c6, c0, 0 9.77 + 9.78 + @ Region 1 - System ROM 9.79 + ldr r0,=( PAGE_64K | 0xFFFF0000 | 1) 9.80 + mcr p15, 0, r0, c6, c1, 0 9.81 + 9.82 + @ Region 2 - alternate vector base 9.83 + ldr r0,=( PAGE_4K | 0x00000000 | 1) 9.84 + mcr p15, 0, r0, c6, c2, 0 9.85 + 9.86 + @ Region 5 - DTCM 9.87 + ldr r0,=__dtcm_start 9.88 + orr r0,r0,#(PAGE_16K | 1) 9.89 + mcr p15, 0, r0, c6, c5, 0 9.90 + 9.91 + @ Region 4 - ITCM 9.92 + ldr r0,=__itcm_start 9.93 + 9.94 + @ align to 32k boundary 9.95 + mov r0,r0,lsr #15 9.96 + mov r0,r0,lsl #15 9.97 + 9.98 + orr r0,r0,#(PAGE_32K | 1) 9.99 + mcr p15, 0, r0, c6, c4, 0 9.100 + 9.101 + ldr r0,=0x4004008 9.102 + ldr r0,[r0] 9.103 + tst r0,#0x8000 9.104 + bne dsi_mode 9.105 + 9.106 + swi 0xf0000 9.107 + 9.108 + ldr r1,=( PAGE_128M | 0x08000000 | 1) 9.109 + cmp r0,#0 9.110 + bne debug_mode 9.111 + 9.112 + ldr r3,=( PAGE_4M | 0x02000000 | 1) 9.113 + ldr r2,=( PAGE_16M | 0x02000000 | 1) 9.114 + mov r8,#0x02400000 9.115 + 9.116 + ldr r9,=dsmasks 9.117 + b setregions 9.118 + 9.119 +debug_mode: 9.120 + ldr r3,=( PAGE_8M | 0x02000000 | 1) 9.121 + ldr r2,=( PAGE_8M | 0x02800000 | 1) 9.122 + mov r8,#0x02800000 9.123 + ldr r9,=debugmasks 9.124 + b setregions 9.125 + 9.126 +dsi_mode: 9.127 + tst r0,#0x4000 9.128 + ldr r1,=( PAGE_8M | 0x03000000 | 1) 9.129 + ldr r3,=( PAGE_16M | 0x02000000 | 1) 9.130 + ldreq r2,=( PAGE_16M | 0x0C000000 | 1) 9.131 + ldrne r2,=( PAGE_32M | 0x0C000000 | 1) @ DSi debugger extended iwram 9.132 + mov r8,#0x03000000 9.133 + ldr r9,=dsimasks 9.134 + 9.135 +setregions: 9.136 + @ Region 3 - DS Accessory (GBA Cart) / DSi switchable iwram 9.137 + mcr p15, 0, r1, c6, c3, 0 9.138 + 9.139 + @ Region 6 - non cacheable main ram 9.140 + mcr p15, 0, r2, c6, c6, 0 9.141 + 9.142 + @ Region 7 - cacheable main ram 9.143 + mcr p15, 0, r3, c6, c7, 0 9.144 + 9.145 + 9.146 + @ Write buffer enable 9.147 + ldr r0,=0b10000000 9.148 + mcr p15, 0, r0, c3, c0, 0 9.149 + 9.150 + @ DCache & ICache enable 9.151 + ldr r0,=0b10000010 9.152 + mcr p15, 0, r0, c2, c0, 0 9.153 + mcr p15, 0, r0, c2, c0, 1 9.154 + 9.155 + @ IAccess 9.156 + ldr r0,=0x33333363 9.157 + mcr p15, 0, r0, c5, c0, 3 9.158 + 9.159 + @ DAccess 9.160 + mcr p15, 0, r0, c5, c0, 2 9.161 + 9.162 + @ Enable ICache, DCache, ITCM & DTCM 9.163 + mrc p15, 0, r0, c1, c0, 0 9.164 + ldr r1,= ITCM_ENABLE | DTCM_ENABLE | ICACHE_ENABLE | DCACHE_ENABLE | PROTECT_ENABLE 9.165 + orr r0,r0,r1 9.166 + mcr p15, 0, r0, c1, c0, 0 9.167 + 9.168 + ldr r0,=masks 9.169 + str r9,[r0] 9.170 + 9.171 + bx lr 9.172 + 9.173 + .global memCached 9.174 + .align 2 9.175 +memCached: 9.176 + ldr r1,=masks 9.177 + ldr r1, [r1] 9.178 + ldr r2,[r1],#4 9.179 + and r0,r0,r2 9.180 + ldr r2,[r1] 9.181 + orr r0,r0,r2 9.182 + bx lr 9.183 + 9.184 + .global memUncached 9.185 + .align 2 9.186 +memUncached: 9.187 + ldr r1,=masks 9.188 + ldr r1, [r1] 9.189 + ldr r2,[r1],#8 9.190 + and r0,r0,r2 9.191 + ldr r2,[r1] 9.192 + orr r0,r0,r2 9.193 + bx lr 9.194 + 9.195 + .data 9.196 + .align 2 9.197 + 9.198 +dsmasks: 9.199 + .word 0x003fffff, 0x02000000, 0x02c00000 9.200 +debugmasks: 9.201 + .word 0x007fffff, 0x02000000, 0x02800000 9.202 +dsimasks: 9.203 + .word 0x00ffffff, 0x02000000, 0x0c000000 9.204 + 9.205 +masks: .word dsmasks 9.206 +