# HG changeset patch
# User John Tsiombikas <nuclear@member.fsf.org>
# Date 1517089080 -7200
# Node ID ab2afb70001aa7996dc34f368995ce69e5503b4a

initial commit test1 without libnds

diff -r 000000000000 -r ab2afb70001a .hgignore
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/.hgignore	Sat Jan 27 23:38:00 2018 +0200
@@ -0,0 +1,7 @@
+\.o$
+\.d$
+\.swp$
+\.elf$
+\.bin$
+\.nds$
+\.bmp$
diff -r 000000000000 -r ab2afb70001a Makefile
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/Makefile	Sat Jan 27 23:38:00 2018 +0200
@@ -0,0 +1,45 @@
+csrc = $(wildcard src/*.c)
+ssrc = src/startup/arm9entry.s $(wildcard src/*.s)
+Ssrc = $(wildcard src/startup/*.S) $(wildcard src/*.S)
+obj = $(csrc:.c=.o) $(ssrc:.s=.o) $(Ssrc:.S=.o)
+
+csrc-arm7 = $(wildcard src/arm7/*.c)
+ssrc-arm7 = src/startup/arm7entry.s $(wildcard src/arm7/*.s)
+obj-arm7 = $(csrc-arm7:.c=.o) $(ssrc-arm7:.s=.o)
+
+name = test1
+bin = $(name).nds
+
+ARCH = arm-none-eabi-
+CPP = $(ARCH)cpp
+CC = $(ARCH)gcc
+AS = $(ARCH)as
+OBJCOPY = $(ARCH)objcopy
+
+EMU = desmume-cli
+
+opt = -fomit-frame-pointer -mcpu=arm946e-s -mtune=arm946e-s
+dbg = -g
+
+CFLAGS = -mthumb $(opt) $(dbg)
+LDFLAGS = -nostartfiles -Wl,--gc-sections -lm
+
+$(bin): arm9.elf arm7.elf data/icon.bmp
+	ndstool -c $@ -9 arm9.elf -7 arm7.elf -b data/icon.bmp "$(name);mindlapse"
+
+arm9.elf: $(obj)
+	$(CC) -o $@ $(obj) -Wl,-T,ds_arm9.mem -Wl,-T,ds_arm9.ld $(LDFLAGS)
+
+arm7.elf: $(obj-arm7)
+	$(CC) -o $@ $(obj-arm7) -Wl,-T,ds_arm7.ld $(LDFLAGS)
+
+.PHONY: clean
+clean:
+	rm -f $(obj) $(obj-arm7) $(bin) arm9.elf arm7.elf $(dep)
+
+.PHONY: simrun
+simrun: $(bin)
+	$(EMU) $(EMUFLAGS) $(bin)
+
+data/icon.bmp: data/icon.bmp.base64
+	base64 -d $< >$@
diff -r 000000000000 -r ab2afb70001a data/icon.bmp.base64
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/data/icon.bmp.base64	Sat Jan 27 23:38:00 2018 +0200
@@ -0,0 +1,37 @@
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diff -r 000000000000 -r ab2afb70001a src/arm7/main.c
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/src/arm7/main.c	Sat Jan 27 23:38:00 2018 +0200
@@ -0,0 +1,4 @@
+int main(void)
+{
+	for(;;);
+}
diff -r 000000000000 -r ab2afb70001a src/dsregs.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/src/dsregs.h	Sat Jan 27 23:38:00 2018 +0200
@@ -0,0 +1,360 @@
+#ifndef DSREGS_H_
+#define DSREGS_H_
+
+#include <stdint.h>
+
+#define REG_BASE		0x4000000
+#define REG8(x)			(*(volatile int8_t*)(REG_BASE + (x)))
+#define REG16(x)		(*(volatile int16_t*)(REG_BASE + (x)))
+#define REG32(x)		(*(volatile int32_t*)(REG_BASE + (x)))
+#define REG64(x)		(*(volatile int64_t*)(REG_BASE + (x)))
+
+/* ---- display engine A ---- */
+#define REG_DISPCNT		REG32(0x00)
+#define REG_DISPSTAT	REG16(0x04)
+#define REG_VCOUNT		REG16(0x06)
+#define REG_BG0CNT		REG16(0x08)
+#define REG_BG1CNT		REG16(0x0a)
+#define REG_BG2CNT		REG16(0x0c)
+#define REG_BG3CNT		REG16(0x0e)
+/* scrolling registers */
+#define REG_BG0HOFS		REG16(0x10)
+#define REG_BG0VOFS		REG16(0x12)
+#define REG_BG1HOFS		REG16(0x14)
+#define REG_BG1VOFS		REG16(0x16)
+#define REG_BG2HOFS		REG16(0x18)
+#define REG_BG2VOFS		REG16(0x1a)
+#define REG_BG3HOFS		REG16(0x1c)
+#define REG_BG3VOFS		REG16(0x1e)
+/* BG rotation and scaling registers */
+#define REG_BG2PA		REG16(0x20)
+#define REG_BG2PB		REG16(0x22)
+#define REG_BG2PC		REG16(0x24)
+#define REG_BG2PD		REG16(0x26)
+#define REG_BG2X		REG32(0x28)
+#define REG_BG2Y		REG32(0x2c)
+#define REG_BG3PA		REG16(0x30)
+#define REG_BG3PB		REG16(0x32)
+#define REG_BG3PC		REG16(0x34)
+#define REG_BG3PD		REG16(0x36)
+#define REG_BG3X		REG32(0x38)
+#define REG_BG3Y		REG32(0x3c)
+/* window registers */
+#define REG_WIN0H		REG16(0x40)
+#define REG_WIN1H		REG16(0x42)
+#define REG_WIN0V		REG16(0x44)
+#define REG_WIN1V		REG16(0x46)
+#define REG_WININ		REG16(0x48)
+#define REG_WINOUT		REG16(0x4a)
+/* mosaic */
+#define REG_MOSAIC		REG16(0x4c)
+/* color effects */
+#define REG_BLDCNT		REG16(0x50)
+#define REG_BLDALPHA	REG16(0x52)
+#define REG_BLDY		REG16(0x54)
+
+#define REG_DISP3DCNT		REG16(0x60)
+#define REG_DISPCAPCNT		REG32(0x64)
+#define REG_DISP_MMEM_FIFO	REG32(0x68)
+#define REG_MASTER_BRIGHT	REG16(0x6c)
+
+/* ---- display engine B ---- */
+#define REG_B_DISPCNT		REG32(0x1000)
+#define REG_B_BG0CNT		REG16(0x1008)
+#define REG_B_BG1CNT		REG16(0x100a)
+#define REG_B_BG2CNT		REG16(0x100c)
+#define REG_B_BG3CNT		REG16(0x100e)
+/* scrolling registers */
+#define REG_B_BG0HOFS		REG16(0x1010)
+#define REG_B_BG0VOFS		REG16(0x1012)
+#define REG_B_BG1HOFS		REG16(0x1014)
+#define REG_B_BG1VOFS		REG16(0x1016)
+#define REG_B_BG2HOFS		REG16(0x1018)
+#define REG_B_BG2VOFS		REG16(0x101a)
+#define REG_B_BG3HOFS		REG16(0x101c)
+#define REG_B_BG3VOFS		REG16(0x101e)
+/* BG rotation and scaling registers */
+#define REG_B_BG2PA			REG16(0x1020)
+#define REG_B_BG2PB			REG16(0x1022)
+#define REG_B_BG2PC			REG16(0x1024)
+#define REG_B_BG2PD			REG16(0x1026)
+#define REG_B_BG2X			REG32(0x1028)
+#define REG_B_BG2Y			REG32(0x102c)
+#define REG_B_BG3PA			REG16(0x1030)
+#define REG_B_BG3PB			REG16(0x1032)
+#define REG_B_BG3PC			REG16(0x1034)
+#define REG_B_BG3PD			REG16(0x1036)
+#define REG_B_BG3X			REG32(0x1038)
+#define REG_B_BG3Y			REG32(0x103c)
+/* window registers */
+#define REG_B_WIN0H			REG16(0x1040)
+#define REG_B_WIN1H			REG16(0x1042)
+#define REG_B_WIN0V			REG16(0x1044)
+#define REG_B_WIN1V			REG16(0x1046)
+#define REG_B_WININ			REG16(0x1048)
+#define REG_B_WINOUT		REG16(0x104a)
+/* mosaic */
+#define REG_B_MOSAIC		REG16(0x104c)
+/* color effects */
+#define REG_B_BLDCNT		REG16(0x1050)
+#define REG_B_BLDALPHA		REG16(0x1052)
+#define REG_B_BLDY			REG16(0x1054)
+
+#define REG_B_MASTER_BRIGHT	REG16(0x106c)
+
+
+#define DISPCNT_BGMODE(x)		(x)
+#define DISPCNT_MODE(x)			((uint32_t)(x) << 16)
+#define DISPCNT_BG0_3D			0x00000008
+#define DISPCNT_TILE_OBJ_1DMAP	0x00000010
+#define DISPCNT_BM_OBJ_256X256	0x00000020
+#define DISPCNT_BM_OBJ_1DMAP	0x00000040
+#define DISPCNT_BLANK			0x00000080
+#define DISPCNT_BG0				0x00000100
+#define DISPCNT_BG1				0x00000200
+#define DISPCNT_BG2				0x00000400
+#define DISPCNT_BG3				0x00000800
+#define DISPCNT_OBJ				0x00001000
+#define DISPCNT_WIN0			0x00002000
+#define DISPCNT_WIN1			0x00004000
+#define DISPCNT_OBJWIN			0x00008000
+
+#define BGXCNT_PRIO(x)			(x)
+#define BGXCNT_CHARBASE(x)		((x) << 2)
+#define BGXCNT_MOSAIC			0x0040
+#define BGXCNT_COL_256			0x0080
+#define BGXCNT_BM				0x0080
+#define BGXCNT_SCRBASE(x)		((x) << 8)
+#define BGXCNT_OVF_WRAP			0x2000
+#define BGXCNT_SCRSIZE(x)		((x) << 14)
+#define BGXCNT_TX_256X256		BGXCNT_SCRSIZE(0)
+#define BGXCNT_TX_512X256		BGXCNT_SCRSIZE(1)
+#define BGXCNT_TX_256X512		BGXCNT_SCRSIZE(2)
+#define BGXCNT_TX_512X512		BGXCNT_SCRSIZE(3)
+#define BGXCNT_RS_128X128		BGXCNT_SCRSIZE(0)
+#define BGXCNT_RS_256X256		BGXCNT_SCRSIZE(1)
+#define BGXCNT_RS_512X512		BGXCNT_SCRSIZE(2)
+#define BGXCNT_RS_1024X1024		BGXCNT_SCRSIZE(3)
+#define BGXCNT_BM_128X128		(BGXCNT_SCRSIZE(0) | BGXCNT_BM)
+#define BGXCNT_BM_256X256		(BGXCNT_SCRSIZE(1) | BGXCNT_BM)
+#define BGXCNT_BM_512X256		(BGXCNT_SCRSIZE(2) | BGXCNT_BM)
+#define BGXCNT_BM_512X512		(BGXCNT_SCRSIZE(3) | BGXCNT_BM)
+#define BGXCNT_BM8				0
+#define BGXCNT_BM16				0x0004
+
+#define VRAM_OFFSET(x)		((x) << 3)
+#define VRAM_ENABLE			0x80
+
+/* ---- DMA registers ---- */
+#define REG_DMA0SAD		REG32(0xb0)
+#define REG_DMA0DAD		REG32(0xb4)
+#define REG_DMA0CNT_L	REG16(0xb8)
+#define REG_DMA0CNT_H	REG16(0xba)
+#define REG_DMA1SAD		REG32(0xbc)
+#define REG_DMA1DAD		REG32(0xc0)
+#define REG_DMA1CNT_L	REG16(0xc4)
+#define REG_DMA1CNT_H	REG16(0xc6)
+#define REG_DMA2SAD		REG32(0xc8)
+#define REG_DMA2DAD		REG32(0xcc)
+#define REG_DMA2CNT_L	REG16(0xd0)
+#define REG_DMA2CNT_H	REG16(0xd2)
+#define REG_DMA3SAD		REG32(0xd4)
+#define REG_DMA3DAD		REG32(0xd8)
+#define REG_DMA3CNT_L	REG16(0xdc)
+#define REG_DMA3CNT_H	REG16(0xde)
+#define REG_DMA0FILL	REG32(0xe0)
+#define REG_DMA1FILL	REG32(0xe4)
+#define REG_DMA2FILL	REG32(0xe8)
+#define REG_DMA3FILL	REG32(0xec)
+
+/* ---- timer registers ---- */
+#define REG_TM0CNT_L	REG16(0x100)
+#define REG_TM0CNT_H	REG16(0x102)
+#define REG_TM1CNT_L	REG16(0x104)
+#define REG_TM1CNT_H	REG16(0x106)
+#define REG_TM2CNT_L	REG16(0x108)
+#define REG_TM2CNT_H	REG16(0x10a)
+#define REG_TM3CNT_L	REG16(0x10c)
+#define REG_TM3CNT_H	REG16(0x10e)
+
+/* ---- keypad registers ---- */
+#define REG_KEYINPUT	REG16(0x130)
+#define REG_KEYCNT		REG16(0x132)
+
+/* ---- IPC/ROM registers ---- */
+#define REG_IPCSYNC		REG16(0x180)
+#define REG_IPCFIFOCNT	REG16(0x184)
+#define REG_IPCFIFOSEND	REG32(0x188)
+#define REG_AUXSPICNT	REG16(0x1a0)
+#define REG_AUXSPIDATA	REG16(0x1a2)
+#define REG_GCARDCNT	REG32(0x1a4)
+#define REG_GCARDCMD64	REG64(0x1a8)
+#define REG_GCARDSEED0	REG32(0x1b0)
+#define REG_GCARDSEED1	REG32(0x1b4)
+#define REG_GCARDSEED0X	REG16(0x1b8)
+#define REG_GCARDSEED1X	REG16(0x1ba)
+
+/* ---- memory & IRQ control registers ---- */
+#define REG_EXMEMCNT	REG16(0x204)
+#define REG_IME			REG16(0x208)
+#define REG_IE			REG32(0x210)
+#define REG_IF			REG32(0x214)
+#define REG_VRAMCNT_A	REG8(0x240)
+#define REG_VRAMCNT_B	REG8(0x241)
+#define REG_VRAMCNT_C	REG8(0x242)
+#define REG_VRAMCNT_D	REG8(0x243)
+#define REG_VRAMCNT_E	REG8(0x244)
+#define REG_VRAMCNT_F	REG8(0x245)
+#define REG_VRAMCNT_G	REG8(0x246)
+#define REG_WRAMCNT		REG8(0x247)
+#define REG_VRAMCNT_H	REG8(0x248)
+#define REG_VRAMCNT_I	REG8(0x249)
+
+/* ---- math hardware registers ---- */
+#define REG_DIVCNT		REG16(0x280)
+#define REG_DIV_NUMER	REG64(0x290)
+#define REG_DIV_DENOM	REG64(0x298)
+#define REG_DIV_RESULT	REG64(0x2a0)
+#define REG_DIVREM_RESULT	REG64(0x2a8)
+#define REG_SQRTCNT		REG16(0x2b0)
+#define REG_SQRT_RESULT	REG32(0x2b4)
+#define REG_SQRT_PARAM	REG64(0x2b8)
+#define REG_POSTFLG		REG32(0x300)
+#define REG_POWCNT1		REG16(0x304)
+#define REG_POWCNT2		REG16(0x304)
+
+#define POWCNT1_LCD			0x0001
+#define POWCNT1_2DA			0x0002
+#define POWCNT1_3DREND		0x0004
+#define POWCNT1_3DGEOM		0x0008
+#define POWCNT1_2DB			0x0200
+#define POWCNT1_DSWAP		0x8000
+
+#define POWCNT2_SOUND		0x0001
+#define POWCNT2_WIFI		0x0002
+
+/* ---- sound registers ---- */
+#define REG_SOUNDXCNT(x)	REG32(0x400 | ((x) << 4))
+#define REG_SOUNDXSAD(x)	REG32(0x404 | ((x) << 4))
+#define REG_SOUNDXTMR(x)	REG32(0x408 | ((x) << 4))
+#define REG_SOUNDXPNT(x)	REG32(0x40a | ((x) << 4))
+#define REG_SOUNDXLEN(x)	REG32(0x40c | ((x) << 4))
+#define REG_SOUNDCNT		REG32(0x500)
+#define REG_SOUNDBIAS		REG32(0x504)
+
+/* ---- 3D hardware registers ---- */
+/* rendering engine */
+#define REG_RDLINES_COUNR	REG8(0x320)
+#define REG_EDGE_COLOR0		REG16(0x330)
+#define REG_EDGE_COLOR1		REG16(0x332)
+#define REG_EDGE_COLOR2		REG16(0x334)
+#define REG_EDGE_COLOR3		REG16(0x336)
+#define REG_EDGE_COLOR4		REG16(0x338)
+#define REG_EDGE_COLOR5		REG16(0x33a)
+#define REG_EDGE_COLOR6		REG16(0x33c)
+#define REG_EDGE_COLOR7		REG16(0x33e)
+#define REG_ALPHA_TEST_REF	REG8(0x340)
+#define REG_CLEAR_COLOR		REG32(0x350)
+#define REG_CLEAR_DEPTH		REG16(0x354)
+#define REG_CLRIMAGE_OFFSET	REG16(0x356)
+#define REG_FOG_COLOR		REG32(0x358)
+#define REG_FOG_OFFSET		REG16(0x35c)
+#define FOG_TABLE_ADDR		((uint8_t*)(REG_BASE + 0x360))
+#define TOON_TABLE_ADDR		((uint16_t*)(REG_BASE + 0x380))
+/* geometry engine */
+#define GXFIFO_ADDR			((uint8_t*)(REG_BASE + 0x400))
+#define REG_GXSTAT			REG32(0x600)
+#define REG_RAM_COUNT		REG32(0x604)
+#define REG_DISP_1DOT_DEPTH	REG16(0x610)
+#define POS_RESULT_ADDR		((uint8_t*)(REG_BASE + 0x620))
+#define VEC_RESULT_ADDR		((uint8_t*)(REG_BASE + 0x630))
+#define CLIPMTX_RESULT_ADDR	((uint32_t*)(REG_BASE + 0x640))
+#define VECMTX_RESULT_ADDR	((uint32_t*)(REG_BASE + 0x680))
+/* geometry command ports */
+#define REG_MTX_MODE		REG32(0x440)	/* 1 */
+#define REG_MTX_PUSH		REG32(0x444)	/* 0 */
+#define REG_MTX_POP			REG32(0x448)	/* 1 */
+#define REG_MTX_STORE		REG32(0x44c)	/* 1 */
+#define REG_MTX_RESTORE		REG32(0x450)	/* 1 */
+#define REG_MTX_IDENTITY	REG32(0x454)	/* 0 */
+#define REG_MTX_LOAD_4X4	REG32(0x458)	/* 16 */
+#define REG_MTX_LOAD_4X3	REG32(0x45c)	/* 12 */
+#define REG_MTX_MULT_4X4	REG32(0x460)	/* 16 */
+#define REG_MTX_MULT_4X3	REG32(0x464)	/* 12 */
+#define REG_MTX_MULT_3X3	REG32(0x468)	/* 9 */
+#define REG_MTX_SCALE		REG32(0x46c)	/* 3 */
+#define REG_MTX_TRANS		REG32(0x470)	/* 3 */
+#define REG_COLOR			REG32(0x480)	/* 1 */
+#define REG_NORMAL			REG32(0x484)	/* 1 */
+#define REG_TEXCOORD		REG32(0x488)	/* 1 */
+#define REG_VTX_16			REG32(0x48c)	/* 2 */
+#define REG_VTX_10			REG32(0x490)	/* 1 */
+#define REG_VTX_XY			REG32(0x494)	/* 1 */
+#define REG_VTX_XZ			REG32(0x498)	/* 1 */
+#define REG_VTX_YZ			REG32(0x49c)	/* 1 */
+#define REG_VTX_DIFF		REG32(0x4a0)	/* 1 */
+#define REG_POLYGON_ATTR	REG32(0x4a4)	/* 1 */
+#define REG_TEXIMAGE_PARAM	REG32(0x4a8)	/* 1 */
+#define REG_PLTT_BASE		REG32(0x4ac)	/* 1 */
+#define REG_DIF_AMB			REG32(0x4c0)	/* 1 */
+#define REG_SPE_EMI			REG32(0x4c4)	/* 1 */
+#define REG_LIGHT_VECTOR	REG32(0x4c8)	/* 1 */
+#define REG_LIGHT_COLOR		REG32(0x4cc)	/* 1 */
+#define REG_SHININESS		REG32(0x4d0)	/* 32 */
+#define REG_BEGIN_VTXS		REG32(0x500)	/* 1 */
+#define REG_END_VTXS		REG32(0x504)	/* 0 */
+#define REG_SWAP_BUFFERS	REG32(0x540)	/* 1 */
+#define REG_VIEWPORT		REG32(0x580)	/* 1 */
+#define REG_BOX_TEST		REG32(0x5c0)	/* 3 */
+#define REG_POS_TEST		REG32(0x5c4)	/* 2 */
+#define REG_VEC_TEST		REG32(0x5c8)	/* 1 */
+
+/* geometry commands */
+#define GCMD_MTX_MODE		0x10	/* 1 */
+#define GCMD_MTX_PUSH		0x11	/* 0 */
+#define GCMD_MTX_POP		0x12	/* 1 */
+#define GCMD_MTX_STORE		0x13	/* 1 */
+#define GCMD_MTX_RESTORE	0x14	/* 1 */
+#define GCMD_MTX_IDENTITY	0x15	/* 0 */
+#define GCMD_MTX_LOAD_4X4	0x16	/* 16 */
+#define GCMD_MTX_LOAD_4X3	0x17	/* 12 */
+#define GCMD_MTX_MULT_4X4	0x18	/* 16 */
+#define GCMD_MTX_MULT_4X3	0x19	/* 12 */
+#define GCMD_MTX_MULT_3X3	0x1a	/* 9 */
+#define GCMD_MTX_SCALE		0x1b	/* 3 */
+#define GCMD_MTX_TRANS		0x1c	/* 3 */
+#define GCMD_COLOR			0x20	/* 1 */
+#define GCMD_NORMAL			0x21	/* 1 */
+#define GCMD_TEXCOORD		0x22	/* 1 */
+#define GCMD_VTX_16			0x23	/* 2 */
+#define GCMD_VTX_10			0x24	/* 1 */
+#define GCMD_VTX_XY			0x25	/* 1 */
+#define GCMD_VTX_XZ			0x26	/* 1 */
+#define GCMD_VTX_YZ			0x27	/* 1 */
+#define GCMD_VTX_DIFF		0x28	/* 1 */
+#define GCMD_POLYGON_ATTR	0x29	/* 1 */
+#define GCMD_TEXIMAGE_PARAM	0x2a	/* 1 */
+#define GCMD_PLTT_BASE		0x2b	/* 1 */
+#define GCMD_DIF_AMB		0x30	/* 1 */
+#define GCMD_SPE_EMI		0x31	/* 1 */
+#define GCMD_LIGHT_VECTOR	0x32	/* 1 */
+#define GCMD_LIGHT_COLOR	0x33	/* 1 */
+#define GCMD_SHININESS		0x34	/* 32 */
+#define GCMD_BEGIN_VTXS		0x40	/* 1 */
+#define GCMD_END_VTXS		0x41	/* 0 */
+#define GCMD_SWAP_BUFFERS	0x50	/* 1 */
+#define GCMD_VIEWPORT		0x60	/* 1 */
+#define GCMD_BOX_TEST		0x70	/* 3 */
+#define GCMD_POS_TEST		0x71	/* 2 */
+#define GCMD_VEC_TEST		0x72	/* 1 */
+
+/* addresses of interest */
+#define SHARED_WRAM_PTR		((void*)0x3000000)
+#define VRAM_BGA_PTR		((void*)0x6000000)
+#define VRAM_BGB_PTR		((void*)0x6200000)
+#define VRAM_OBJA_PTR		((void*)0x6400000)
+#define VRAM_OBJB_PTR		((void*)0x6600000)
+#define VRAM_LCDC_PTR		((void*)0x6800000)
+#define OAM_PTR				((void*)0x7000000)
+
+#endif	/* DSREGS_H_ */
diff -r 000000000000 -r ab2afb70001a src/main.c
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/src/main.c	Sat Jan 27 23:38:00 2018 +0200
@@ -0,0 +1,68 @@
+#include <stdint.h>
+#include <math.h>
+#include "dsregs.h"
+
+static void xorpat(void *addr, int xsz, int ysz);
+
+static void *vram = VRAM_LCDC_PTR;
+static uint16_t *bgmem = VRAM_BGB_PTR;
+
+int main(void)
+{
+	uint32_t frame;
+
+	REG_POWCNT1 = POWCNT1_LCD | POWCNT1_2DA | POWCNT1_2DB | POWCNT1_DSWAP;
+
+	REG_DISPCNT = DISPCNT_MODE(2);
+	REG_B_DISPCNT = DISPCNT_MODE(1) | DISPCNT_BG2 | 5;
+
+	REG_B_BG2CNT = BGXCNT_BM_256X256 | BGXCNT_BM16 | BGXCNT_OVF_WRAP;
+	REG_B_BG2PA = 0x100;
+	REG_B_BG2PB = 0;
+	REG_B_BG2PC = 0;
+	REG_B_BG2PD = 0x100;
+
+	REG_VRAMCNT_A = VRAM_ENABLE;
+	REG_VRAMCNT_C = VRAM_ENABLE | 4;
+
+	xorpat(vram, 256, 192);
+	xorpat(bgmem, 256, 256);
+
+	for(;;) {
+		float t = (float)frame * 0.00035;
+		float scale = 0.5 * sin(t * 0.8) + 0.8;
+		int32_t sa = (int16_t)(sin(t) * 256 * scale);
+		int32_t ca = (int16_t)(cos(t) * 256 * scale);
+
+		int32_t x = ca * -128 + sa * -96 + (128 << 8);
+		int32_t y = -sa * -128 + ca * -96 + (96 << 8);
+
+		while(REG_VCOUNT < 192);
+
+		REG_B_BG2PA = ca;
+		REG_B_BG2PB = sa;
+		REG_B_BG2PC = -sa;
+		REG_B_BG2PD = ca;
+		REG_B_BG2X = x;
+		REG_B_BG2Y = y;
+
+		++frame;
+	}
+	return 0;
+}
+
+static void xorpat(void *addr, int xsz, int ysz)
+{
+	int i, j;
+	uint16_t *p = addr;
+
+	for(i=0; i<ysz; i++) {
+		for(j=0; j<xsz; j++) {
+			int xor = i^j;
+			uint16_t red = xor >> 2;
+			uint16_t green = xor >> 1;
+			uint16_t blue = xor;
+			*p++ = 0x8000 | red | ((green & 0x1f) << 5) | ((blue & 0x1f) << 10);
+		}
+	}
+}
diff -r 000000000000 -r ab2afb70001a src/startup/arm7entry.s
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/src/startup/arm7entry.s	Sat Jan 27 23:38:00 2018 +0200
@@ -0,0 +1,175 @@
+@ vi:set filetype=armasm:
+	.section ".crt0","ax"
+	.global _start
+	.align	4
+	.arm
+_start:
+	mov	r0, #0x04000000		@ IME = 0;
+	mov	r1, #0
+	str	r1, [r0, #0x208]
+
+	mov	r0, #0x12		@ Switch to IRQ Mode
+	msr	cpsr, r0
+	ldr	sp, =__sp_irq		@ Set IRQ stack
+
+	mov	r0, #0x13		@ Switch to SVC Mode
+	msr	cpsr, r0
+	ldr	sp, =__sp_svc		@ Set SVC stack
+
+	mov	r0, #0x1F		@ Switch to System Mode
+	msr	cpsr, r0
+	ldr	sp, =__sp_usr		@ Set user stack
+
+#ifndef VRAM
+	adr	r1, __sync_start	@ Perform ARM7<->ARM9 sync code
+	ldr	r2, =__arm7_start__
+	mov	r3, #(__sync_end-__sync_start)
+	mov	r8, r2
+	bl	CopyMem
+	mov	r3, r8
+	bl	_blx_r3_stub
+
+@ Copy arm7 binary from LMA to VMA (EWRAM to IWRAM)
+	adr	r0, arm7lma		@ Calculate ARM7 LMA
+	ldr	r1, [r0]
+	add	r1, r1, r0
+	ldr	r2, =__arm7_start__
+	ldr	r4, =__arm7_end__
+	bl	CopyMemCheck
+
+#else
+	bl	__sync_start
+#endif
+
+	ldr	r0, =__bss_start__	@ Clear BSS section to 0x00
+	ldr	r1, =__bss_end__
+	sub	r1, r1, r0
+	bl	ClearMem
+
+#ifndef VRAM
+	cmp	r10, #1
+	bne	NotTWL
+	ldr	r1, =__dsimode		@ set DSi mode flag
+	strb	r10, [r1]
+
+	ldr	r1, =0x02ffe1d8		@ Get ARM7i LMA from header
+	ldr	r1, [r1]
+	ldr	r2, =__arm7i_start__
+	ldr	r4, =__arm7i_end__
+	bl	CopyMemCheck
+
+	ldr	r0, =__twl_bss_start__	@ Clear TWL BSS section to 0x00
+	ldr	r1, =__twl_bss_end__
+	sub	r1, r1, r0
+	bl	ClearMem
+#endif
+
+NotTWL:
+	mov	r0, #0			@ int argc
+	mov	r1, #0			@ char *argv[]
+	ldr	r3, =main
+	mov	r12, #0x4000000		@ tell arm9 we are ready
+	mov	r9, #0
+	str	r9, [r12, #0x180]
+_blx_r3_stub:
+	bx	r3
+infloop:
+	b infloop
+
+#ifndef VRAM
+arm7lma:
+	.word	__arm7_lma__ - .
+#endif
+	.pool
+
+@---------------------------------------------------------------------------------
+@ ARM7<->ARM9 synchronization code
+@---------------------------------------------------------------------------------
+
+__sync_start:
+	push	{lr}
+	mov	r12, #0x4000000
+	mov	r9, #0x0
+	bl	IPCSync
+	mov	r9, #(0x9<<8)
+	str	r9, [r12, #0x180]
+	mov	r9, #0xA
+	bl	IPCSync
+	mov	r9, #(0xB<<8)
+	str	r9, [r12, #0x180]
+	mov	r9, #0xC
+	bl	IPCSync
+	mov	r9, #(0xD<<8)
+	str	r9, [r12, #0x180]
+IPCRecvFlag:
+	ldr	r10, [r12, #0x180]
+	and	r10, r10, #0xF
+	cmp	r10, #0xC
+	beq	IPCRecvFlag
+	pop	{pc}
+IPCSync:
+	ldr	r10, [r12, #0x180]
+	and	r10, r10, #0xF
+	cmp	r10, r9
+	bne	IPCSync
+	bx	lr
+__sync_end:
+
+@---------------------------------------------------------------------------------
+@ Clear memory to 0x00 if length != 0
+@  r0 = Start Address
+@  r1 = Length
+@---------------------------------------------------------------------------------
+ClearMem:
+@---------------------------------------------------------------------------------
+	mov	r2, #3			@ Round down to nearest word boundary
+	add	r1, r1, r2		@ Shouldn't be needed
+	bics	r1, r1, r2		@ Clear 2 LSB (and set Z)
+	bxeq	lr			@ Quit if copy size is 0
+
+	mov	r2, #0
+ClrLoop:
+	stmia	r0!, {r2}
+	subs	r1, r1, #4
+	bne	ClrLoop
+	bx	lr
+
+@---------------------------------------------------------------------------------
+@ Copy memory if length	!= 0
+@  r1 = Source Address
+@  r2 = Dest Address
+@  r4 = Dest Address + Length
+@---------------------------------------------------------------------------------
+CopyMemCheck:
+@---------------------------------------------------------------------------------
+	cmp	r1, r2
+	bxeq	lr
+
+	sub	r3, r4, r2		@ Is there any data to copy?
+@---------------------------------------------------------------------------------
+@ Copy memory
+@  r1 = Source Address
+@  r2 = Dest Address
+@  r3 = Length
+@---------------------------------------------------------------------------------
+CopyMem:
+@---------------------------------------------------------------------------------
+	mov	r0, #3			@ These commands are used in cases where
+	add	r3, r3, r0		@ the length is not a multiple of 4,
+	bics	r3, r3, r0		@ even though it should be.
+	bxeq	lr			@ Length is zero, so exit
+CIDLoop:
+	ldmia	r1!, {r0}
+	stmia	r2!, {r0}
+	subs	r3, r3, #4
+	bne	CIDLoop
+	bx	lr
+
+@---------------------------------------------------------------------------------
+	.align
+	.pool
+
+	.global __dsimode
+__dsimode: .word
+	.end
+@---------------------------------------------------------------------------------
diff -r 000000000000 -r ab2afb70001a src/startup/arm9entry.s
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/src/startup/arm9entry.s	Sat Jan 27 23:38:00 2018 +0200
@@ -0,0 +1,192 @@
+@ vi:set filetype=armasm:
+	.arch	armv5te
+	.cpu	arm946e-s
+	.section ".crt0","ax"
+	.global _start
+	.align	4
+	.arm
+_start:
+	mov	r0, #0x04000000		@ IME = 0;
+	str	r0, [r0, #0x208]
+	
+	@ set sensible stacks to allow bios call
+
+	mov	r0, #0x13		@ Switch to SVC Mode
+	msr	cpsr, r0
+	mov	r1,#0x03000000
+	sub	r1,r1,#0x1000
+	mov	sp,r1
+	mov	r0, #0x1F		@ Switch to System Mode
+	msr	cpsr, r0
+	sub	r1,r1,#0x100
+	mov	sp,r1
+
+	ldr	r3, =mpu_setup
+	blx	r3
+
+	mov	r0, #0x12		@ Switch to IRQ Mode
+	msr	cpsr, r0
+	ldr	sp, =__sp_irq		@ Set IRQ stack
+
+	mov	r0, #0x13		@ Switch to SVC Mode
+	msr	cpsr, r0
+	ldr	sp, =__sp_svc		@ Set SVC stack
+
+	mov	r0, #0x1F		@ Switch to System Mode
+	msr	cpsr, r0
+	ldr	sp, =__sp_usr		@ Set user stack
+
+	mov	r12, #0x4000000		@ Read system ROM status (NTR/TWL)
+	ldrb	r11, [r12,r12,lsr #12]
+	and	r11, r11, #0x3
+
+	b skip_sync
+
+	mov	r9, #(0x0<<8)		@ Synchronize with ARM7
+	str	r9, [r12, #0x180]
+	mov	r9, #0x9
+	bl	IPCSync
+	mov	r9, #(0xA<<8)
+	str	r9, [r12, #0x180]
+	mov	r9, #0xB
+	bl	IPCSync
+	mov	r9, #(0xC<<8)
+	str	r9, [r12, #0x180]
+	mov	r9, #0xD
+	bl	IPCSync
+	mov	r9, r11, lsl #8
+	str	r9, [r12, #0x180]
+	mov	r9, #0
+	bl	IPCSync
+	str	r9, [r12, #0x180]
+
+skip_sync:
+
+	ldr	r1, =__itcm_lma		@ Copy instruction tightly coupled memory (itcm section) from LMA to VMA
+	ldr	r2, =__itcm_start
+	ldr	r4, =__itcm_end
+	bl	CopyMemCheck
+
+	ldr	r1, =__vectors_lma	@ Copy reserved vectors area (itcm section) from LMA to VMA
+	ldr	r2, =__vectors_start
+	ldr	r4, =__vectors_end
+	bl	CopyMemCheck
+
+	ldr	r1, =__dtcm_lma		@ Copy data tightly coupled memory (dtcm section) from LMA to VMA
+	ldr	r2, =__dtcm_start
+	ldr	r4, =__dtcm_end
+	bl	CopyMemCheck
+
+	cmp	r11, #1
+	ldrne	r10, =__end__		@ (DS mode) heap start
+	ldreq	r10, =__twl_end__	@ (DSi mode) heap start
+
+	ldr	r0, =__bss_start__	@ Clear BSS section
+	ldr	r1, =__bss_end__
+	sub	r1, r1, r0
+	bl	ClearMem
+
+	ldr	r0, =__sbss_start	@ Clear SBSS section 
+	ldr	r1, =__sbss_end
+	sub	r1, r1, r0
+	bl	ClearMem
+
+	cmp	r11, #1
+	bne	NotTWL
+	ldr	r9, =__dsimode		@ set DSi mode flag
+	strb	r11, [r9]
+
+	@ Copy TWL area (arm9i section) from LMA to VMA
+	ldr	r1, =0x02ffe1c8		@ Get ARM9i LMA from header
+	ldr	r1, [r1]
+
+	ldr	r2, =__arm9i_start__
+	cmp	r1, r2			@ skip copy if LMA=VMA
+	ldrne	r4, =__arm9i_end__
+	blne	CopyMemCheck
+
+	ldr	r0, =__twl_bss_start__	@ Clear TWL BSS section
+	ldr	r1, =__twl_bss_end__
+	sub	r1, r1, r0
+	bl	ClearMem
+
+NotTWL:
+	ldr r0, =__secure_area__
+	ldr	r3, =main
+	bx	r3			@ jump to user code
+infloop:
+	b infloop
+
+
+
+@---------------------------------------------------------------------------------
+@ Clear memory to 0x00 if length != 0
+@  r0 = Start Address
+@  r1 = Length
+@---------------------------------------------------------------------------------
+ClearMem:
+@---------------------------------------------------------------------------------
+	mov	r2, #3			@ Round down to nearest word boundary
+	add	r1, r1, r2		@ Shouldn't be needed
+	bics	r1, r1, r2		@ Clear 2 LSB (and set Z)
+	bxeq	lr			@ Quit if copy size is 0
+
+	mov	r2, #0
+ClrLoop:
+	stmia	r0!, {r2}
+	subs	r1, r1, #4
+	bne	ClrLoop
+
+	bx	lr
+
+@---------------------------------------------------------------------------------
+@ Copy memory if length	!= 0
+@  r1 = Source Address
+@  r2 = Dest Address
+@  r4 = Dest Address + Length
+@---------------------------------------------------------------------------------
+CopyMemCheck:
+@---------------------------------------------------------------------------------
+	sub	r3, r4, r2		@ Is there any data to copy?
+@---------------------------------------------------------------------------------
+@ Copy memory
+@  r1 = Source Address
+@  r2 = Dest Address
+@  r3 = Length
+@---------------------------------------------------------------------------------
+CopyMem:
+@---------------------------------------------------------------------------------
+	mov	r0, #3			@ These commands are used in cases where
+	add	r3, r3, r0		@ the length is not a multiple of 4,
+	bics	r3, r3, r0		@ even though it should be.
+	bxeq	lr			@ Length is zero, so exit
+CIDLoop:
+	ldmia	r1!, {r0}
+	stmia	r2!, {r0}
+	subs	r3, r3, #4
+	bne	CIDLoop
+
+	bx	lr
+
+@ Synchronize with ARM7
+IPCSync:
+	ldr	r10, [r12, #0x180]
+	and	r10, r10, #0xF
+	cmp	r10, r9
+	bne	IPCSync
+	bx	lr
+
+
+	.align
+	.pool
+
+	.data
+	.global __dsimode
+__dsimode:
+	.word 0
+
+	.section ".secure","a"
+	.align 2
+	.global __secure_area__
+__secure_area__:
+	.space 2048, 0
diff -r 000000000000 -r ab2afb70001a src/startup/mpu_setup.S
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/src/startup/mpu_setup.S	Sat Jan 27 23:38:00 2018 +0200
@@ -0,0 +1,203 @@
+@ vi:set filetype=armasm:
+#define PAGE_4K		(0b01011 << 1)
+#define PAGE_8K		(0b01100 << 1)
+#define PAGE_16K	(0b01101 << 1)
+#define PAGE_32K	(0b01110 << 1)
+#define PAGE_64K	(0b01111 << 1)
+#define PAGE_128K	(0b10000 << 1)
+#define PAGE_256K	(0b10001 << 1)
+#define PAGE_512K	(0b10010 << 1)
+#define PAGE_1M		(0b10011 << 1)
+#define PAGE_2M		(0b10100 << 1)
+#define PAGE_4M		(0b10101 << 1)
+#define PAGE_8M		(0b10110 << 1)
+#define PAGE_16M	(0b10111 << 1)
+#define PAGE_32M	(0b11000 << 1)
+#define PAGE_64M	(0b11001 << 1)
+#define PAGE_128M	(0b11010 << 1)
+#define PAGE_256M	(0b11011 << 1)
+#define PAGE_512M	(0b11100 << 1)
+#define PAGE_1G		(0b11101 << 1)
+#define PAGE_2G		(0b11110 << 1)
+#define PAGE_4G		(0b11111 << 1)
+
+#define ITCM_LOAD	(1<<19)
+#define ITCM_ENABLE	(1<<18)
+#define DTCM_LOAD	(1<<17)
+#define DTCM_ENABLE	(1<<16)
+#define DISABLE_TBIT	(1<<15)
+#define ROUND_ROBIN	(1<<14)
+#define ALT_VECTORS	(1<<13)
+#define ICACHE_ENABLE	(1<<12)
+#define BIG_ENDIAN	(1<<7)
+#define DCACHE_ENABLE	(1<<2)
+#define PROTECT_ENABLE	(1<<0)
+
+	.arch	armv5te
+	.cpu	arm946e-s
+
+	.text
+	.arm
+
+	.global mpu_setup
+	.align 2
+mpu_setup:
+@ turn the power on for M3
+	ldr     r1, =0x8203
+	mov	r0, #0x04000000
+	add	r0, r0, #0x304
+	strh    r1, [r0]
+
+	ldr	r1, =0x00002078			@ disable TCM and protection unit
+	mcr	p15, 0, r1, c1, c0
+
+@ Protection Unit Setup added by Sasq
+	@ Disable cache
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c5, 0		@ Instruction cache
+	mcr	p15, 0, r0, c7, c6, 0		@ Data cache
+
+	@ Wait for write buffer to empty
+	mcr	p15, 0, r0, c7, c10, 4
+
+	ldr	r0, =__dtcm_start
+	orr	r0,r0,#0x0a
+	mcr	p15, 0, r0, c9, c1,0		@ DTCM base = __dtcm_start, size = 16 KB
+
+	mov	r0,#0x20
+	mcr	p15, 0, r0, c9, c1,1		@ ITCM base = 0 , size = 32 MB
+
+@ Setup memory regions similar to Release Version
+	@ Region 0 - IO registers
+	ldr	r0,=( PAGE_64M | 0x04000000 | 1)
+	mcr	p15, 0, r0, c6, c0, 0
+
+	@ Region 1 - System ROM
+	ldr	r0,=( PAGE_64K | 0xFFFF0000 | 1)
+	mcr	p15, 0, r0, c6, c1, 0
+
+	@ Region 2 - alternate vector base
+	ldr	r0,=( PAGE_4K | 0x00000000 | 1)
+	mcr	p15, 0, r0, c6, c2, 0
+
+	@ Region 5 - DTCM
+	ldr	r0,=__dtcm_start
+	orr	r0,r0,#(PAGE_16K | 1)
+	mcr	p15, 0, r0, c6, c5, 0
+
+	@ Region 4 - ITCM
+	ldr	r0,=__itcm_start
+
+	@ align to 32k boundary
+	mov	r0,r0,lsr #15
+	mov	r0,r0,lsl #15
+
+	orr	r0,r0,#(PAGE_32K | 1)
+	mcr	p15, 0, r0, c6, c4, 0
+
+	ldr	r0,=0x4004008
+	ldr	r0,[r0]
+	tst	r0,#0x8000
+	bne	dsi_mode
+
+	swi	0xf0000
+
+	ldr	r1,=( PAGE_128M | 0x08000000 | 1)
+	cmp	r0,#0
+	bne	debug_mode
+
+	ldr	r3,=( PAGE_4M | 0x02000000 | 1)
+	ldr	r2,=( PAGE_16M | 0x02000000 | 1)
+	mov	r8,#0x02400000
+
+	ldr	r9,=dsmasks
+	b	setregions
+
+debug_mode:
+	ldr	r3,=( PAGE_8M | 0x02000000 | 1)
+	ldr	r2,=( PAGE_8M | 0x02800000 | 1)
+	mov	r8,#0x02800000
+	ldr	r9,=debugmasks
+	b	setregions
+
+dsi_mode:
+	tst	r0,#0x4000
+	ldr	r1,=( PAGE_8M  | 0x03000000 | 1)
+	ldr	r3,=( PAGE_16M | 0x02000000 | 1)
+	ldreq	r2,=( PAGE_16M | 0x0C000000 | 1)
+	ldrne	r2,=( PAGE_32M | 0x0C000000 | 1) @ DSi debugger extended iwram
+	mov	r8,#0x03000000
+	ldr	r9,=dsimasks
+
+setregions:
+	@ Region 3 - DS Accessory (GBA Cart) / DSi switchable iwram
+	mcr	p15, 0, r1, c6, c3, 0
+
+	@ Region 6 - non cacheable main ram
+	mcr	p15, 0, r2, c6, c6, 0
+
+	@ Region 7 - cacheable main ram
+	mcr	p15, 0, r3, c6, c7, 0
+
+
+	@ Write buffer enable
+	ldr	r0,=0b10000000
+	mcr	p15, 0, r0, c3, c0, 0
+
+	@ DCache & ICache enable
+	ldr	r0,=0b10000010
+	mcr	p15, 0, r0, c2, c0, 0
+	mcr	p15, 0, r0, c2, c0, 1
+
+	@ IAccess
+	ldr	r0,=0x33333363
+	mcr	p15, 0, r0, c5, c0, 3
+
+	@ DAccess
+	mcr     p15, 0, r0, c5, c0, 2
+
+	@ Enable ICache, DCache, ITCM & DTCM
+	mrc	p15, 0, r0, c1, c0, 0
+	ldr	r1,= ITCM_ENABLE | DTCM_ENABLE | ICACHE_ENABLE | DCACHE_ENABLE | PROTECT_ENABLE
+	orr	r0,r0,r1
+	mcr	p15, 0, r0, c1, c0, 0
+
+	ldr	r0,=masks
+	str	r9,[r0]
+
+	bx	lr
+
+	.global memCached
+	.align 2
+memCached:
+	ldr	r1,=masks
+	ldr	r1, [r1]
+	ldr	r2,[r1],#4
+	and	r0,r0,r2
+	ldr	r2,[r1]
+	orr	r0,r0,r2
+	bx	lr
+
+	.global memUncached
+	.align 2
+memUncached:
+	ldr	r1,=masks
+	ldr	r1, [r1]
+	ldr	r2,[r1],#8
+	and	r0,r0,r2
+	ldr	r2,[r1]
+	orr	r0,r0,r2
+	bx	lr
+
+	.data
+	.align	2
+
+dsmasks:
+	.word	0x003fffff, 0x02000000, 0x02c00000
+debugmasks:
+	.word	0x007fffff, 0x02000000, 0x02800000
+dsimasks:
+	.word	0x00ffffff, 0x02000000, 0x0c000000
+
+masks:	.word	dsmasks
+