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1 #ifndef MEGADRIVE_IO_H_
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2 #define MEGADRIVE_IO_H_
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3
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4 #include <stdint.h>
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5
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6 #define IO_REG_VER *((volatile uint8_t*)0xa10001)
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7 #define IO_REG_DATA1 *((volatile uint8_t*)0xa10003)
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8 #define IO_REG_DATA2 *((volatile uint8_t*)0xa10005)
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9 #define IO_REG_DATA3 *((volatile uint8_t*)0xa10007)
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10 #define IO_REG_CTRL1 *((volatile uint8_t*)0xa10009)
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11 #define IO_REG_CTRL2 *((volatile uint8_t*)0xa1000b)
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12 #define IO_REG_CTRL3 *((volatile uint8_t*)0xa1000d)
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13 #define IO_REG_TXDATA1 *((volatile uint8_t*)0xa1000f)
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14 #define IO_REG_RXDATA1 *((volatile uint8_t*)0xa10011)
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15 #define IO_REG_S_CTRL1 *((volatile uint8_t*)0xa10013)
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16 #define IO_REG_TXDATA2 *((volatile uint8_t*)0xa10015)
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17 #define IO_REG_RXDATA2 *((volatile uint8_t*)0xa10017)
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18 #define IO_REG_S_CTRL2 *((volatile uint8_t*)0xa10013)
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19 #define IO_REG_TXDATA3 *((volatile uint8_t*)0xa1001b)
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20 #define IO_REG_RXDATA3 *((volatile uint8_t*)0xa1001d)
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21 #define IO_REG_S_CTRL3 *((volatile uint8_t*)0xa1001f)
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22 #define IO_REG_LOCK *((volatile uint8_t*)0xa14000)
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23 #define IO_REG_TMSS *((volatile uint8_t*)0xa14101)
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24
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25 #define IO_REG_DATA(x) *((volatile uint8_t*)0xa10003 + ((x) << 1))
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26 #define IO_REG_CTRL(x) *((volatile uint8_t*)0xa10009 + ((x) << 1))
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27
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28
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29 enum {
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30 IO_VER_VERSION_MASK = 0x0f,
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31 IO_VER_EXP = 0x20,
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32 IO_VER_PAL = 0x40,
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33 IO_VER_NONJP = 0x80
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34 };
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35
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36 enum {
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37 IO_PAD_UP = 1,
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38 IO_PAD_DOWN = 2,
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39 IO_PAD_LEFT = 4,
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40 IO_PAD_RIGHT = 8,
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41 IO_PAD_B = 16,
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42 IO_PAD_C = 32,
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43 IO_PAD_A = 64,
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44 IO_PAD_START = 128
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45 };
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46
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47 static inline void io_setdir(int port, uint8_t dir)
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48 {
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49 IO_REG_CTRL(port) = dir;
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50 }
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51
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52 static inline uint16_t io_readpad(int port)
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53 {
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54 uint16_t bnstate;
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55
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56 io_setdir(port, 0x40); /* pin 6 (multiplexer) output, 0-5 inputs */
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57 IO_REG_DATA(port) = 0x40; /* select mode 1 */
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58 bnstate = IO_REG_DATA(port);
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59 IO_REG_DATA(port) = 0; /* select mode 0 */
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60 bnstate |= (IO_REG_DATA(port) << 2) & (IO_PAD_A | IO_PAD_START);
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61 return ~bnstate;
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62 }
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63
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64 #endif /* MEGADRIVE_IO_H_ */
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