megadrive_test1

changeset 5:f99eab59e7dc
clarified the C code by using VDP macros
author: John Tsiombikas <nuclear@member.fsf.org>
date: Wed, 01 Feb 2017 14:40:19 +0200
parents: e7138066c7ea
children: 862f8a034cae
files: src/main.c src/vdp.h
diffstat: 2 files changed, 34 insertions(+), 6 deletions(-) [+]
[-]

src/main.c 12

src/vdp.h 28 src/main.c 12 src/vdp.h 28
src/main.c 12
src/vdp.h 28
     1.1 --- a/src/main.c	Wed Feb 01 13:40:50 2017 +0200
     1.2 +++ b/src/main.c	Wed Feb 01 14:40:19 2017 +0200
     1.3 @@ -2,11 +2,11 @@
     1.4  
     1.5  int main(void)
     1.6  {
     1.7 -	VDP_PORT_CTL = 0xc000;
     1.8 -	VDP_PORT_CTL = 0;
     1.9 -	VDP_PORT_DATA = 0x1f8;
    1.10 -	VDP_PORT_CTL = 0x8700;
    1.11 -	VDP_PORT_CTL = 0x8004;
    1.12 -	VDP_PORT_CTL = 0x8144;
    1.13 +	VDP_SET_CRAM_ADDR(0);
    1.14 +	VDP_SET_CRAM_RGB24(64, 128, 255);
    1.15 +	VDP_SET_BGCOLOR(0, 0);
    1.16 +	/* enable display */
    1.17 +	VDP_SET_REG(0, VDP_REG0_BASE);
    1.18 +	VDP_SET_REG(1, VDP_REG1_BASE | VDP_REG1_DISP_BIT);
    1.19  	return 0;
    1.20  }

     2.1 --- a/src/vdp.h	Wed Feb 01 13:40:50 2017 +0200
     2.2 +++ b/src/vdp.h	Wed Feb 01 14:40:19 2017 +0200
     2.3 @@ -30,6 +30,19 @@
     2.4  	(0x8000 | (VDP_CTL_REGSEL_MASK & ((uint16_t)(reg) << 8)) | \
     2.5  	 (VDP_CTL_DATA_MASK & (uint16_t)(val)))
     2.6  
     2.7 +#define VDP_SET_REG(reg, val) \
     2.8 +	do { VDP_PORT_CTL = VDP_RSET(reg, val); } while(0)
     2.9 +
    2.10 +#define VDP_REG0_BASE		4
    2.11 +#define VDP_REG0_HVCNT_BIT	0x02
    2.12 +#define VDP_REG0_HINTR_BIT	0x10
    2.13 +
    2.14 +#define VDP_REG1_BASE		4
    2.15 +#define VDP_REG1_30CELL_BIT	0x08
    2.16 +#define VDP_REG1_DMA_BIT	0x10
    2.17 +#define VDP_REG1_VINTR_BIT	0x20
    2.18 +#define VDP_REG1_DISP_BIT	0x40
    2.19 +
    2.20  #define VDP_MODE_WR_BIT		1
    2.21  
    2.22  #define VDP_VRAM_WR		1
    2.23 @@ -37,5 +50,20 @@
    2.24  
    2.25  #define VDP_ADDRSET(addr, mode) /* TODO */
    2.26  
    2.27 +#define VDP_CRAM_ADDR32(addr) (0xc0000000 | ((uint32_t)(addr) << 16))
    2.28 +
    2.29 +#define VDP_SET_CRAM_ADDR(addr) \
    2.30 +	do { VDP_PORT_CTL32 = VDP_CRAM_ADDR32(addr); } while(0)
    2.31 +
    2.32 +#define VDP_RGB24(r, g, b) \
    2.33 +	((((uint16_t)(r) >> 4) & 0xe) | \
    2.34 +	 ((uint16_t)(g) & 0xe0) | \
    2.35 +	 (((uint16_t)(b) << 4) & 0xe00))
    2.36 +
    2.37 +#define VDP_SET_CRAM_RGB24(r, g, b) \
    2.38 +	do { VDP_PORT_DATA = VDP_RGB24(r, g, b); } while(0)
    2.39 +
    2.40 +#define VDP_SET_BGCOLOR(pal, col) \
    2.41 +	do { VDP_SET_REG(7, ((pal) << 4) | (col)); } while(0)
    2.42  
    2.43  #endif	/* VDP_H_ */