# HG changeset patch
# User John Tsiombikas <nuclear@member.fsf.org>
# Date 1485952819 -7200
# Node ID f99eab59e7dce5142906048e2b262eda28b4a210
# Parent  e7138066c7ea29e891eb20bbea3252de1e996b01
clarified the C code by using VDP macros

diff -r e7138066c7ea -r f99eab59e7dc src/main.c
--- a/src/main.c	Wed Feb 01 13:40:50 2017 +0200
+++ b/src/main.c	Wed Feb 01 14:40:19 2017 +0200
@@ -2,11 +2,11 @@
 
 int main(void)
 {
-	VDP_PORT_CTL = 0xc000;
-	VDP_PORT_CTL = 0;
-	VDP_PORT_DATA = 0x1f8;
-	VDP_PORT_CTL = 0x8700;
-	VDP_PORT_CTL = 0x8004;
-	VDP_PORT_CTL = 0x8144;
+	VDP_SET_CRAM_ADDR(0);
+	VDP_SET_CRAM_RGB24(64, 128, 255);
+	VDP_SET_BGCOLOR(0, 0);
+	/* enable display */
+	VDP_SET_REG(0, VDP_REG0_BASE);
+	VDP_SET_REG(1, VDP_REG1_BASE | VDP_REG1_DISP_BIT);
 	return 0;
 }
diff -r e7138066c7ea -r f99eab59e7dc src/vdp.h
--- a/src/vdp.h	Wed Feb 01 13:40:50 2017 +0200
+++ b/src/vdp.h	Wed Feb 01 14:40:19 2017 +0200
@@ -30,6 +30,19 @@
 	(0x8000 | (VDP_CTL_REGSEL_MASK & ((uint16_t)(reg) << 8)) | \
 	 (VDP_CTL_DATA_MASK & (uint16_t)(val)))
 
+#define VDP_SET_REG(reg, val) \
+	do { VDP_PORT_CTL = VDP_RSET(reg, val); } while(0)
+
+#define VDP_REG0_BASE		4
+#define VDP_REG0_HVCNT_BIT	0x02
+#define VDP_REG0_HINTR_BIT	0x10
+
+#define VDP_REG1_BASE		4
+#define VDP_REG1_30CELL_BIT	0x08
+#define VDP_REG1_DMA_BIT	0x10
+#define VDP_REG1_VINTR_BIT	0x20
+#define VDP_REG1_DISP_BIT	0x40
+
 #define VDP_MODE_WR_BIT		1
 
 #define VDP_VRAM_WR		1
@@ -37,5 +50,20 @@
 
 #define VDP_ADDRSET(addr, mode) /* TODO */
 
+#define VDP_CRAM_ADDR32(addr) (0xc0000000 | ((uint32_t)(addr) << 16))
+
+#define VDP_SET_CRAM_ADDR(addr) \
+	do { VDP_PORT_CTL32 = VDP_CRAM_ADDR32(addr); } while(0)
+
+#define VDP_RGB24(r, g, b) \
+	((((uint16_t)(r) >> 4) & 0xe) | \
+	 ((uint16_t)(g) & 0xe0) | \
+	 (((uint16_t)(b) << 4) & 0xe00))
+
+#define VDP_SET_CRAM_RGB24(r, g, b) \
+	do { VDP_PORT_DATA = VDP_RGB24(r, g, b); } while(0)
+
+#define VDP_SET_BGCOLOR(pal, col) \
+	do { VDP_SET_REG(7, ((pal) << 4) | (col)); } while(0)
 
 #endif	/* VDP_H_ */