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view src/intr.c @ 49:50730d42d2d3

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fuck yeah, now do priviledge levels and TSS
author John Tsiombikas <nuclear@member.fsf.org>
date Sat, 30 Jul 2011 07:21:54 +0300
parents e6de3c6015cb
children b1e8c8251884
line source
1 #include <stdio.h>
2 #include "intr.h"
3 #include "desc.h"
4 #include "segm.h"
5 #include "asmops.h"
6 #include "panic.h"
7
8 /* IDT gate descriptor bits */
9 #define GATE_TASK (5 << 8)
10 #define GATE_INTR (6 << 8)
11 #define GATE_TRAP (7 << 8)
12 #define GATE_DEFAULT (1 << 11)
13 #define GATE_PRESENT (1 << 15)
14
15 /* PIC command and data ports */
16 #define PIC1_CMD 0x20
17 #define PIC1_DATA 0x21
18 #define PIC2_CMD 0xa0
19 #define PIC2_DATA 0xa1
20
21 /* PIC initialization command word 1 bits */
22 #define ICW1_ICW4_NEEDED (1 << 0)
23 #define ICW1_SINGLE (1 << 1)
24 #define ICW1_INTERVAL4 (1 << 2)
25 #define ICW1_LEVEL (1 << 3)
26 #define ICW1_INIT (1 << 4)
27 /* PIC initialization command word 4 bits */
28 #define ICW4_8086 (1 << 0)
29 #define ICW4_AUTO_EOI (1 << 1)
30 #define ICW4_BUF_SLAVE (1 << 3) /* 1000 */
31 #define ICW4_BUF_MASTER (3 << 2) /* 1100 */
32 #define ICW4_SPECIAL (1 << 4)
33
34 /* PIC operation command word 2 bits */
35 #define OCW2_EOI (1 << 5)
36
37
38 static void init_pic(int offset);
39 static void gate_desc(desc_t *desc, uint16_t sel, uint32_t addr, int dpl, int type);
40 static void set_intr_entry(int num, void (*handler)(void));
41 static void end_of_irq(int irq);
42
43 /* defined in intr-asm.S */
44 void set_idt(uint32_t addr, uint16_t limit);
45 void intr_entry_default(void);
46
47 /* the IDT (interrupt descriptor table) */
48 static desc_t idt[256];
49 /* table of handler functions for all interrupts */
50 static intr_func_t intr_func[256];
51
52
53 void init_intr(void)
54 {
55 int i;
56
57 set_idt((uint32_t)idt, sizeof idt - 1);
58
59 /* initialize all entry points and interrupt handlers */
60 for(i=0; i<256; i++) {
61 set_intr_entry(i, intr_entry_default);
62 interrupt(i, 0);
63 }
64
65 /* by including interrupts.h here (without ASM being defined)
66 * the series of INTR_ENTRY_* macros will be expanded to a series
67 * of function prototypes for all interrupt entry points and the
68 * corresponding calls to set_intr_entry to set up the IDT slots
69 */
70 #include "interrupts.h"
71
72 /* initialize the programmable interrupt controller
73 * setting up the maping of IRQs [0, 15] to interrupts [32, 47]
74 */
75 init_pic(IRQ_OFFSET);
76 }
77
78 /* set an interrupt handler function for a particular interrupt */
79 void interrupt(int intr_num, intr_func_t func)
80 {
81 intr_func[intr_num] = func;
82 }
83
84 /* this function is called from all interrupt entry points
85 * it calls the appropriate interrupt handlers if available and handles
86 * sending an end-of-interrupt command to the PICs when finished.
87 */
88 void dispatch_intr(struct intr_frame frm)
89 {
90 if(intr_func[frm.inum]) {
91 intr_func[frm.inum](frm.inum, frm.err);
92 } else {
93 if(frm.inum < 32) {
94 panic("unhandled exception %d, error code: %d\n", frm.inum, frm.err);
95 }
96 printf("unhandled interrupt %d\n", frm.inum);
97 }
98
99 if(IS_IRQ(frm.inum)) {
100 end_of_irq(INTR_TO_IRQ(frm.inum));
101 }
102 }
103
104 static void init_pic(int offset)
105 {
106 /* send ICW1 saying we'll follow with ICW4 later on */
107 outb(ICW1_INIT | ICW1_ICW4_NEEDED, PIC1_CMD);
108 outb(ICW1_INIT | ICW1_ICW4_NEEDED, PIC2_CMD);
109 /* send ICW2 with IRQ remapping */
110 outb(offset, PIC1_DATA);
111 outb(offset + 8, PIC2_DATA);
112 /* send ICW3 to setup the master/slave relationship */
113 /* ... set bit3 = 3rd interrupt input has a slave */
114 outb(4, PIC1_DATA);
115 /* ... set slave ID to 2 */
116 outb(2, PIC2_DATA);
117 /* send ICW4 to set 8086 mode (no calls generated) */
118 outb(ICW4_8086, PIC1_DATA);
119 outb(ICW4_8086, PIC2_DATA);
120 /* done, just reset the data port to 0 */
121 outb(0, PIC1_DATA);
122 outb(0, PIC2_DATA);
123 }
124
125 static void gate_desc(desc_t *desc, uint16_t sel, uint32_t addr, int dpl, int type)
126 {
127 /* first 16bit part is the low 16bits of the entry address */
128 desc->d[0] = addr & 0xffff;
129 /* second 16bit part is the segment selector for the entry code */
130 desc->d[1] = sel;
131 /* third 16bit part has the privilege level, type, and present bit */
132 desc->d[2] = ((dpl & 3) << 13) | type | GATE_DEFAULT | GATE_PRESENT;
133 /* last 16bit part is the high 16bits of the entry address */
134 desc->d[3] = (addr & 0xffff0000) >> 16;
135 }
136
137 #define IS_TRAP(n) ((n) >= 32 && !IS_IRQ(n))
138 static void set_intr_entry(int num, void (*handler)(void))
139 {
140 int type = IS_TRAP(num) ? GATE_TRAP : GATE_INTR;
141 gate_desc(idt + num, selector(SEGM_KCODE, 0), (uint32_t)handler, 0, type);
142 }
143
144 static void end_of_irq(int irq)
145 {
146 if(irq > 7) {
147 outb(OCW2_EOI, PIC2_CMD);
148 }
149 outb(OCW2_EOI, PIC1_CMD);
150 }