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view src/intr.c @ 42:e6de3c6015cb

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started implementing processes
author John Tsiombikas <nuclear@member.fsf.org>
date Sun, 24 Jul 2011 18:29:24 +0300
parents 928b0ebfff4d
children f65b348780e3
line source
1 #include <stdio.h>
2 #include "intr.h"
3 #include "desc.h"
4 #include "segm.h"
5 #include "asmops.h"
6 #include "panic.h"
7
8 /* IDT gate descriptor bits */
9 #define GATE_TASK (5 << 8)
10 #define GATE_INTR (6 << 8)
11 #define GATE_TRAP (7 << 8)
12 #define GATE_DEFAULT (1 << 11)
13 #define GATE_PRESENT (1 << 15)
14
15 /* PIC command and data ports */
16 #define PIC1_CMD 0x20
17 #define PIC1_DATA 0x21
18 #define PIC2_CMD 0xa0
19 #define PIC2_DATA 0xa1
20
21 /* PIC initialization command word 1 bits */
22 #define ICW1_ICW4_NEEDED (1 << 0)
23 #define ICW1_SINGLE (1 << 1)
24 #define ICW1_INTERVAL4 (1 << 2)
25 #define ICW1_LEVEL (1 << 3)
26 #define ICW1_INIT (1 << 4)
27 /* PIC initialization command word 4 bits */
28 #define ICW4_8086 (1 << 0)
29 #define ICW4_AUTO_EOI (1 << 1)
30 #define ICW4_BUF_SLAVE (1 << 3) /* 1000 */
31 #define ICW4_BUF_MASTER (3 << 2) /* 1100 */
32 #define ICW4_SPECIAL (1 << 4)
33
34 /* PIC operation command word 2 bits */
35 #define OCW2_EOI (1 << 5)
36
37
38 /* structure used to pass the interrupt stack frame from the
39 * entry points to the C dispatch function.
40 */
41 struct intr_frame {
42 /* registers pushed by pusha in intr_entry_* */
43 struct registers regs;
44 /* interrupt number and error code pushed in intr_entry_* */
45 uint32_t inum, err;
46 /* pushed by CPU during interrupt entry */
47 uint32_t eip, cs, eflags;
48 /* pushed by CPU during interrupt entry from user space */
49 uint32_t esp, ss;
50 };
51
52
53 static void init_pic(int offset);
54 static void gate_desc(desc_t *desc, uint16_t sel, uint32_t addr, int dpl, int type);
55 static void set_intr_entry(int num, void (*handler)(void));
56 static void end_of_irq(int irq);
57
58 /* defined in intr-asm.S */
59 void set_idt(uint32_t addr, uint16_t limit);
60 void intr_entry_default(void);
61
62 /* the IDT (interrupt descriptor table) */
63 static desc_t idt[256];
64 /* table of handler functions for all interrupts */
65 static intr_func_t intr_func[256];
66
67
68 void init_intr(void)
69 {
70 int i;
71
72 set_idt((uint32_t)idt, sizeof idt - 1);
73
74 /* initialize all entry points and interrupt handlers */
75 for(i=0; i<256; i++) {
76 set_intr_entry(i, intr_entry_default);
77 interrupt(i, 0);
78 }
79
80 /* by including interrupts.h here (without ASM being defined)
81 * the series of INTR_ENTRY_* macros will be expanded to a series
82 * of function prototypes for all interrupt entry points and the
83 * corresponding calls to set_intr_entry to set up the IDT slots
84 */
85 #include "interrupts.h"
86
87 /* initialize the programmable interrupt controller
88 * setting up the maping of IRQs [0, 15] to interrupts [32, 47]
89 */
90 init_pic(IRQ_OFFSET);
91 }
92
93 /* set an interrupt handler function for a particular interrupt */
94 void interrupt(int intr_num, intr_func_t func)
95 {
96 intr_func[intr_num] = func;
97 }
98
99 /* this function is called from all interrupt entry points
100 * it calls the appropriate interrupt handlers if available and handles
101 * sending an end-of-interrupt command to the PICs when finished.
102 */
103 void dispatch_intr(struct intr_frame frm)
104 {
105 if(intr_func[frm.inum]) {
106 intr_func[frm.inum](frm.inum, frm.err);
107 } else {
108 if(frm.inum < 32) {
109 panic("unhandled exception %d, error code: %d\n", frm.inum, frm.err);
110 }
111 printf("unhandled interrupt %d\n", frm.inum);
112 }
113
114 if(IS_IRQ(frm.inum)) {
115 end_of_irq(INTR_TO_IRQ(frm.inum));
116 }
117 }
118
119 static void init_pic(int offset)
120 {
121 /* send ICW1 saying we'll follow with ICW4 later on */
122 outb(ICW1_INIT | ICW1_ICW4_NEEDED, PIC1_CMD);
123 outb(ICW1_INIT | ICW1_ICW4_NEEDED, PIC2_CMD);
124 /* send ICW2 with IRQ remapping */
125 outb(offset, PIC1_DATA);
126 outb(offset + 8, PIC2_DATA);
127 /* send ICW3 to setup the master/slave relationship */
128 /* ... set bit3 = 3rd interrupt input has a slave */
129 outb(4, PIC1_DATA);
130 /* ... set slave ID to 2 */
131 outb(2, PIC2_DATA);
132 /* send ICW4 to set 8086 mode (no calls generated) */
133 outb(ICW4_8086, PIC1_DATA);
134 outb(ICW4_8086, PIC2_DATA);
135 /* done, just reset the data port to 0 */
136 outb(0, PIC1_DATA);
137 outb(0, PIC2_DATA);
138 }
139
140 static void gate_desc(desc_t *desc, uint16_t sel, uint32_t addr, int dpl, int type)
141 {
142 /* first 16bit part is the low 16bits of the entry address */
143 desc->d[0] = addr & 0xffff;
144 /* second 16bit part is the segment selector for the entry code */
145 desc->d[1] = sel;
146 /* third 16bit part has the privilege level, type, and present bit */
147 desc->d[2] = ((dpl & 3) << 13) | type | GATE_DEFAULT | GATE_PRESENT;
148 /* last 16bit part is the high 16bits of the entry address */
149 desc->d[3] = (addr & 0xffff0000) >> 16;
150 }
151
152 #define IS_TRAP(n) ((n) >= 32 && !IS_IRQ(n))
153 static void set_intr_entry(int num, void (*handler)(void))
154 {
155 int type = IS_TRAP(num) ? GATE_TRAP : GATE_INTR;
156 gate_desc(idt + num, selector(SEGM_KCODE, 0), (uint32_t)handler, 0, type);
157 }
158
159 static void end_of_irq(int irq)
160 {
161 if(irq > 7) {
162 outb(OCW2_EOI, PIC2_CMD);
163 }
164 outb(OCW2_EOI, PIC1_CMD);
165 }