kern
view src/ata.c @ 87:178d5a95e6de
implementing ata read
| author | John Tsiombikas <nuclear@member.fsf.org> |
|---|---|
| date | Wed, 07 Dec 2011 17:10:37 +0200 |
| parents | 379332fc1667 |
| children | a398bf73fe93 |
line source
1 #include <stdio.h>
2 #include <stdlib.h>
3 #include <string.h>
4 #include <ctype.h>
5 #include <inttypes.h>
6 #include <assert.h>
7 #include "ata.h"
8 #include "intr.h"
9 #include "asmops.h"
10 #include "sched.h"
11 #include "mutex.h"
13 /* registers */
14 #define REG_DATA 0 /* R/W */
15 #define REG_ERROR 1 /* R */
16 #define REG_FEATURES 1 /* W */
17 #define REG_COUNT 2 /* R/W */
18 #define REG_LBA0 3 /* R/W */
19 #define REG_LBA1 4 /* R/W */
20 #define REG_LBA2 5 /* R/W */
21 #define REG_DEVICE 6 /* R/W */
22 #define REG_CMD 7 /* W */
23 #define REG_STATUS 7 /* R */
25 #define REG_CTL 518
26 #define REG_ALTSTAT 518
28 /* status bit fields */
29 #define ST_ERR (1 << 0)
30 #define ST_DRQ (1 << 3)
31 #define ST_DRDY (1 << 6)
32 #define ST_BSY (1 << 7)
34 /* device select bit in control register */
35 #define DEV_SEL(x) (((x) & 1) << 4)
36 #define DEV_LBA (1 << 6)
38 /* ATA commands */
39 #define CMD_IDENTIFY 0xec
40 #define CMD_READ 0x20
41 #define CMD_READ48 0x24
42 #define CMD_WRITE 0x30
43 #define CMD_WRITE48 0x34
46 struct device {
47 int id; /* id of the device on its ATA interface (0 master, 1 slave) */
48 int iface; /* ATA interface for this device (0 or 1) */
49 int port_base; /* interface I/O port base */
51 uint32_t nsect_lba;
52 uint64_t nsect_lba48;
53 };
56 static int identify(struct device *dev, int iface, int id);
57 static void select_dev(struct device *dev);
58 static int wait_busy(struct device *dev);
59 static int wait_drq(struct device *dev);
60 static void read_data(struct device *dev, void *buf);
61 static inline uint8_t read_reg8(struct device *dev, int reg);
62 static inline uint16_t read_reg16(struct device *dev, int reg);
63 static inline void write_reg8(struct device *dev, int reg, uint8_t val);
64 static inline void write_reg16(struct device *dev, int reg, uint16_t val);
65 static void ata_intr(int inum);
66 static void *atastr(void *res, void *src, int n);
67 static char *size_str(uint64_t nsect, char *buf);
68 static void print_error(int devid, int wr, uint32_t high, uint32_t low, unsigned char err);
70 /* last drive selected on each bus */
71 static int drvsel[2] = {-1, -1};
73 /* 4 possible devices: 2 ATA interfaces with 2 devices each.
74 * this will never change unless we start querying the PCI config space
75 * for additional drives (in which case this whole init code must be
76 * rewritten anyway), but I like it spelt out like this.
77 */
78 #define MAX_IFACES 2
79 #define MAX_DEV (MAX_IFACES * 2)
80 static struct device devices[MAX_DEV];
82 static int use_irq;
84 /* This serves as a sync point for I/O. While the mutex is held,
85 * some process is doing I/O and all the others must wait.
86 */
87 static mutex_t pending;
90 void init_ata(void)
91 {
92 int i;
94 interrupt(IRQ_TO_INTR(15), ata_intr);
96 for(i=0; i<MAX_DEV; i++) {
97 int iface = i / MAX_IFACES;
98 int id = i % MAX_IFACES;
100 if(identify(devices + i, iface, id) == -1) {
101 devices[i].id = -1;
102 }
103 }
105 /* init code done, from now on use the irq sleep/wakeup mechanism */
106 use_irq = 1;
107 }
109 int ata_read_pio(int devno, uint64_t sect, void *buf)
110 {
111 int cmd, st, res = -1;
112 uint32_t sect_low, sect_high;
113 struct device *dev = devices + devno;
115 if(dev->id == -1) {
116 return -1;
117 }
119 if(use_irq) {
120 /* wait for the interface to become available */
121 mutex_lock(&pending);
122 }
124 select_dev(dev);
126 /* LBA48 requires the high-order bits first */
127 if(sect >= dev->nsect_lba) {
128 sect_high = (uint32_t)(sect >> 24);
129 sect_low = (uint32_t)sect & 0xffffff;
131 if(sect >= dev->nsect_lba48) {
132 goto end;
133 }
134 cmd = CMD_READ48;
136 write_reg8(dev, REG_COUNT, 0);
137 write_reg8(dev, REG_LBA0, sect_high & 0xff);
138 write_reg8(dev, REG_LBA1, (sect_high >> 8) & 0xff);
139 write_reg8(dev, REG_LBA2, (sect_high >> 16) & 0xff);
140 } else {
141 cmd = CMD_READ;
142 sect_high = 0;
143 sect_low = (uint32_t)sect & 0xfffffff;
144 }
146 write_reg8(dev, REG_COUNT, 1);
147 write_reg8(dev, REG_LBA0, sect_low & 0xff);
148 write_reg8(dev, REG_LBA1, (sect_low >> 8) & 0xff);
149 write_reg8(dev, REG_LBA2, (sect_low >> 16) & 0xff);
150 write_reg8(dev, REG_DEVICE, ((sect_low >> 24) & 0xf) | DEV_LBA | DEV_SEL(dev->id));
151 /* execute */
152 write_reg8(dev, REG_CMD, cmd);
154 /* wait for the data to become available */
155 do {
156 if(use_irq) {
157 /* also sleep on the mutex if we're called from userspace */
158 wait(&pending);
159 }
160 } while(((st = read_reg8(dev, REG_ALTSTAT)) & (ST_DRQ | ST_ERR)) == 0);
162 if(st & ST_ERR) {
163 //print_error(int devid, int wr, uint32_t high, uint32_t low, unsigned char err);
164 unsigned char err;
166 err = read_reg8(dev, REG_ERROR);
167 print_error(devno, 0, sect_high, sect_low, err);
168 goto end;
169 }
171 /* read the data and we're done */
172 read_data(dev, buf);
173 res = 0;
174 end:
175 if(use_irq) {
176 mutex_unlock(&pending);
177 }
178 return res;
179 }
181 int ata_write_pio(int devno, uint64_t sect, void *buf)
182 {
183 if(devices[devno].id == -1) {
184 return -1;
185 }
186 return -1;
187 }
189 static int identify(struct device *dev, int iface, int id)
190 {
191 /* base address of the two ATA interfaces */
192 static const int port_base[] = {0x1f0, 0x170};
193 unsigned char st;
194 uint16_t *info;
195 char textbuf[42]; /* at most we need 40 chars for ident strings */
197 dev->id = id;
198 dev->iface = iface;
199 dev->port_base = port_base[iface];
201 /* a status of 0xff means there's no drive on the interface */
202 if((st = read_reg8(dev, REG_ALTSTAT)) == 0xff) {
203 return -1;
204 }
206 select_dev(dev);
208 write_reg8(dev, REG_CMD, CMD_IDENTIFY);
210 if(!(st = read_reg8(dev, REG_ALTSTAT)) || (st & ST_ERR)) {
211 /* does not exist */
212 return -1;
213 }
214 if(wait_busy(dev) == -1) {
215 /* got ST_ERR, not ATA */
216 return -1;
217 }
219 info = malloc(512);
220 assert(info);
222 /* read the device information */
223 read_data(dev, info);
225 /* print model and serial */
226 printf("ata%d: %s", (dev->iface << 1) | dev->id, atastr(textbuf, info + 27, 40));
227 printf(" [s/n: %s]", atastr(textbuf, info + 10, 20));
229 dev->nsect_lba = *(uint32_t*)(info + 60);
230 dev->nsect_lba48 = *(uint64_t*)(info + 100) & 0xffffffffffffull;
232 if(!dev->nsect_lba) {
233 printf(" drive does not support LBA, ignoring!\n");
234 free(info);
235 return -1;
236 }
238 if(dev->nsect_lba48) {
239 size_str(dev->nsect_lba48, textbuf);
240 } else {
241 size_str(dev->nsect_lba, textbuf);
242 }
243 printf(" size: %s\n", textbuf);
245 free(info);
246 return 0;
247 }
249 static void select_dev(struct device *dev)
250 {
251 /* if this is the currently selected device, thy work is done */
252 if(drvsel[dev->iface] == dev->id)
253 return;
255 /* wait for BSY and DRQ to clear */
256 while(read_reg8(dev, REG_ALTSTAT) & (ST_BSY | ST_DRQ));
258 /* set the correct device bit to the device register */
259 write_reg8(dev, REG_DEVICE, DEV_SEL(dev->id));
261 /* wait a bit to allow the device time to respond */
262 iodelay(); iodelay(); iodelay(); iodelay();
263 }
265 static int wait_busy(struct device *dev)
266 {
267 unsigned char st;
269 do {
270 st = read_reg8(dev, REG_ALTSTAT);
271 } while((st & ST_BSY) && !(st & ST_ERR));
273 return st & ST_ERR ? -1 : 0;
274 }
276 static int wait_drq(struct device *dev)
277 {
278 unsigned char st;
280 do {
281 st = read_reg8(dev, REG_ALTSTAT);
282 } while(!(st & (ST_DRQ | ST_ERR)));
284 return st & ST_ERR ? -1 : 0;
285 }
287 static void read_data(struct device *dev, void *buf)
288 {
289 int i;
290 uint16_t *ptr = buf;
292 /* wait for the data request from the drive */
293 wait_drq(dev);
295 /* ready to transfer */
296 for(i=0; i<256; i++) {
297 *ptr++ = read_reg16(dev, REG_DATA);
298 }
299 }
301 static inline uint8_t read_reg8(struct device *dev, int reg)
302 {
303 uint8_t val;
304 inb(val, dev->port_base + reg);
305 return val;
306 }
308 static inline uint16_t read_reg16(struct device *dev, int reg)
309 {
310 uint16_t val;
311 inw(val, dev->port_base + reg);
312 return val;
313 }
315 static inline void write_reg8(struct device *dev, int reg, uint8_t val)
316 {
317 outb(val, dev->port_base + reg);
318 }
320 static inline void write_reg16(struct device *dev, int reg, uint16_t val)
321 {
322 outw(val, dev->port_base + reg);
323 }
325 static void ata_intr(int inum)
326 {
327 printf("ATA interrupt\n");
328 }
330 static void *atastr(void *res, void *src, int n)
331 {
332 int i;
333 uint16_t *sptr = (uint16_t*)src;
334 char *dptr = res;
336 for(i=0; i<n/2; i++) {
337 *dptr++ = (*sptr & 0xff00) >> 8;
338 *dptr++ = *sptr++ & 0xff;
339 }
341 while(isspace(*--dptr));
342 *++dptr = 0;
343 return res;
344 }
346 static char *size_str(uint64_t nsect, char *buf)
347 {
348 static const char *suffix[] = {"kb", "mb", "gb", "tb", "pb", 0};
349 int i;
350 unsigned int rem;
352 /* start with kilobytes */
353 nsect /= 2;
355 for(i=0; nsect >= 1024 && suffix[i + 1]; i++) {
356 rem = nsect % 1024;
357 nsect /= 1024;
358 }
359 sprintf(buf, "%u.%u%s", (unsigned int)nsect, 100 * rem / 1024, suffix[i]);
360 return buf;
361 }
363 #define ERR_NM (1 << 1)
364 #define ERR_ABRT (1 << 2)
365 #define ERR_MCR (1 << 3)
366 #define ERR_IDNF (1 << 4)
367 #define ERR_MC (1 << 5)
368 #define ERR_UNC (1 << 6)
370 static void print_error(int devid, int wr, uint32_t high, uint32_t low, unsigned char err)
371 {
372 printf("ata%d %s %serror ", devid, wr ? "write" : "read", err & ERR_UNC ? "uncorrectable " : "");
373 printf("at sector %x%x: ", high, low);
375 if(err & ERR_ABRT)
376 printf("abort ");
377 if(err & ERR_IDNF)
378 printf("invalid address ");
379 if(err & ERR_NM)
380 printf("no media ");
382 printf("(%x)\n", (unsigned int)err);
383 }