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annotate src/intr.c @ 42:e6de3c6015cb

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started implementing processes
author John Tsiombikas <nuclear@member.fsf.org>
date Sun, 24 Jul 2011 18:29:24 +0300
parents 928b0ebfff4d
children f65b348780e3
rev   line source
nuclear@11 1 #include <stdio.h>
nuclear@11 2 #include "intr.h"
nuclear@11 3 #include "desc.h"
nuclear@11 4 #include "segm.h"
nuclear@11 5 #include "asmops.h"
nuclear@11 6 #include "panic.h"
nuclear@11 7
nuclear@11 8 /* IDT gate descriptor bits */
nuclear@11 9 #define GATE_TASK (5 << 8)
nuclear@11 10 #define GATE_INTR (6 << 8)
nuclear@11 11 #define GATE_TRAP (7 << 8)
nuclear@11 12 #define GATE_DEFAULT (1 << 11)
nuclear@11 13 #define GATE_PRESENT (1 << 15)
nuclear@11 14
nuclear@11 15 /* PIC command and data ports */
nuclear@11 16 #define PIC1_CMD 0x20
nuclear@11 17 #define PIC1_DATA 0x21
nuclear@11 18 #define PIC2_CMD 0xa0
nuclear@11 19 #define PIC2_DATA 0xa1
nuclear@11 20
nuclear@11 21 /* PIC initialization command word 1 bits */
nuclear@11 22 #define ICW1_ICW4_NEEDED (1 << 0)
nuclear@11 23 #define ICW1_SINGLE (1 << 1)
nuclear@11 24 #define ICW1_INTERVAL4 (1 << 2)
nuclear@11 25 #define ICW1_LEVEL (1 << 3)
nuclear@11 26 #define ICW1_INIT (1 << 4)
nuclear@11 27 /* PIC initialization command word 4 bits */
nuclear@11 28 #define ICW4_8086 (1 << 0)
nuclear@11 29 #define ICW4_AUTO_EOI (1 << 1)
nuclear@11 30 #define ICW4_BUF_SLAVE (1 << 3) /* 1000 */
nuclear@11 31 #define ICW4_BUF_MASTER (3 << 2) /* 1100 */
nuclear@11 32 #define ICW4_SPECIAL (1 << 4)
nuclear@11 33
nuclear@11 34 /* PIC operation command word 2 bits */
nuclear@11 35 #define OCW2_EOI (1 << 5)
nuclear@11 36
nuclear@11 37
nuclear@11 38 /* structure used to pass the interrupt stack frame from the
nuclear@11 39 * entry points to the C dispatch function.
nuclear@11 40 */
nuclear@11 41 struct intr_frame {
nuclear@11 42 /* registers pushed by pusha in intr_entry_* */
nuclear@42 43 struct registers regs;
nuclear@11 44 /* interrupt number and error code pushed in intr_entry_* */
nuclear@11 45 uint32_t inum, err;
nuclear@11 46 /* pushed by CPU during interrupt entry */
nuclear@11 47 uint32_t eip, cs, eflags;
nuclear@42 48 /* pushed by CPU during interrupt entry from user space */
nuclear@42 49 uint32_t esp, ss;
nuclear@11 50 };
nuclear@11 51
nuclear@11 52
nuclear@11 53 static void init_pic(int offset);
nuclear@11 54 static void gate_desc(desc_t *desc, uint16_t sel, uint32_t addr, int dpl, int type);
nuclear@11 55 static void set_intr_entry(int num, void (*handler)(void));
nuclear@11 56 static void end_of_irq(int irq);
nuclear@11 57
nuclear@11 58 /* defined in intr-asm.S */
nuclear@11 59 void set_idt(uint32_t addr, uint16_t limit);
nuclear@11 60 void intr_entry_default(void);
nuclear@11 61
nuclear@11 62 /* the IDT (interrupt descriptor table) */
nuclear@11 63 static desc_t idt[256];
nuclear@11 64 /* table of handler functions for all interrupts */
nuclear@11 65 static intr_func_t intr_func[256];
nuclear@11 66
nuclear@11 67
nuclear@11 68 void init_intr(void)
nuclear@11 69 {
nuclear@11 70 int i;
nuclear@11 71
nuclear@11 72 set_idt((uint32_t)idt, sizeof idt - 1);
nuclear@11 73
nuclear@11 74 /* initialize all entry points and interrupt handlers */
nuclear@11 75 for(i=0; i<256; i++) {
nuclear@11 76 set_intr_entry(i, intr_entry_default);
nuclear@11 77 interrupt(i, 0);
nuclear@11 78 }
nuclear@11 79
nuclear@11 80 /* by including interrupts.h here (without ASM being defined)
nuclear@11 81 * the series of INTR_ENTRY_* macros will be expanded to a series
nuclear@11 82 * of function prototypes for all interrupt entry points and the
nuclear@11 83 * corresponding calls to set_intr_entry to set up the IDT slots
nuclear@11 84 */
nuclear@11 85 #include "interrupts.h"
nuclear@11 86
nuclear@11 87 /* initialize the programmable interrupt controller
nuclear@11 88 * setting up the maping of IRQs [0, 15] to interrupts [32, 47]
nuclear@11 89 */
nuclear@11 90 init_pic(IRQ_OFFSET);
nuclear@11 91 }
nuclear@11 92
nuclear@11 93 /* set an interrupt handler function for a particular interrupt */
nuclear@11 94 void interrupt(int intr_num, intr_func_t func)
nuclear@11 95 {
nuclear@11 96 intr_func[intr_num] = func;
nuclear@11 97 }
nuclear@11 98
nuclear@11 99 /* this function is called from all interrupt entry points
nuclear@11 100 * it calls the appropriate interrupt handlers if available and handles
nuclear@11 101 * sending an end-of-interrupt command to the PICs when finished.
nuclear@11 102 */
nuclear@11 103 void dispatch_intr(struct intr_frame frm)
nuclear@11 104 {
nuclear@11 105 if(intr_func[frm.inum]) {
nuclear@11 106 intr_func[frm.inum](frm.inum, frm.err);
nuclear@11 107 } else {
nuclear@11 108 if(frm.inum < 32) {
nuclear@11 109 panic("unhandled exception %d, error code: %d\n", frm.inum, frm.err);
nuclear@11 110 }
nuclear@11 111 printf("unhandled interrupt %d\n", frm.inum);
nuclear@11 112 }
nuclear@11 113
nuclear@11 114 if(IS_IRQ(frm.inum)) {
nuclear@11 115 end_of_irq(INTR_TO_IRQ(frm.inum));
nuclear@11 116 }
nuclear@11 117 }
nuclear@11 118
nuclear@11 119 static void init_pic(int offset)
nuclear@11 120 {
nuclear@11 121 /* send ICW1 saying we'll follow with ICW4 later on */
nuclear@11 122 outb(ICW1_INIT | ICW1_ICW4_NEEDED, PIC1_CMD);
nuclear@11 123 outb(ICW1_INIT | ICW1_ICW4_NEEDED, PIC2_CMD);
nuclear@11 124 /* send ICW2 with IRQ remapping */
nuclear@11 125 outb(offset, PIC1_DATA);
nuclear@11 126 outb(offset + 8, PIC2_DATA);
nuclear@11 127 /* send ICW3 to setup the master/slave relationship */
nuclear@11 128 /* ... set bit3 = 3rd interrupt input has a slave */
nuclear@11 129 outb(4, PIC1_DATA);
nuclear@11 130 /* ... set slave ID to 2 */
nuclear@11 131 outb(2, PIC2_DATA);
nuclear@11 132 /* send ICW4 to set 8086 mode (no calls generated) */
nuclear@11 133 outb(ICW4_8086, PIC1_DATA);
nuclear@11 134 outb(ICW4_8086, PIC2_DATA);
nuclear@11 135 /* done, just reset the data port to 0 */
nuclear@11 136 outb(0, PIC1_DATA);
nuclear@11 137 outb(0, PIC2_DATA);
nuclear@11 138 }
nuclear@11 139
nuclear@11 140 static void gate_desc(desc_t *desc, uint16_t sel, uint32_t addr, int dpl, int type)
nuclear@11 141 {
nuclear@11 142 /* first 16bit part is the low 16bits of the entry address */
nuclear@11 143 desc->d[0] = addr & 0xffff;
nuclear@11 144 /* second 16bit part is the segment selector for the entry code */
nuclear@11 145 desc->d[1] = sel;
nuclear@11 146 /* third 16bit part has the privilege level, type, and present bit */
nuclear@11 147 desc->d[2] = ((dpl & 3) << 13) | type | GATE_DEFAULT | GATE_PRESENT;
nuclear@11 148 /* last 16bit part is the high 16bits of the entry address */
nuclear@11 149 desc->d[3] = (addr & 0xffff0000) >> 16;
nuclear@11 150 }
nuclear@11 151
nuclear@29 152 #define IS_TRAP(n) ((n) >= 32 && !IS_IRQ(n))
nuclear@11 153 static void set_intr_entry(int num, void (*handler)(void))
nuclear@11 154 {
nuclear@11 155 int type = IS_TRAP(num) ? GATE_TRAP : GATE_INTR;
nuclear@11 156 gate_desc(idt + num, selector(SEGM_KCODE, 0), (uint32_t)handler, 0, type);
nuclear@11 157 }
nuclear@11 158
nuclear@11 159 static void end_of_irq(int irq)
nuclear@11 160 {
nuclear@11 161 if(irq > 7) {
nuclear@11 162 outb(OCW2_EOI, PIC2_CMD);
nuclear@11 163 }
nuclear@11 164 outb(OCW2_EOI, PIC1_CMD);
nuclear@11 165 }