amiga_boottest

changeset 1:48093e4bd99a

stuff
author John Tsiombikas <nuclear@member.fsf.org>
date Wed, 21 Feb 2018 18:00:45 +0200
parents 51422ea54b9d
children 58ebd84822e7
files .hgignore Makefile amiga.ld src/boot/boot.s src/copper.c src/copper.h src/hwregs.h src/intr.h src/intr.s src/inttypes.h src/main.c src/startup.s
diffstat 12 files changed, 669 insertions(+), 28 deletions(-) [+]
line diff
     1.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.2 +++ b/.hgignore	Wed Feb 21 18:00:45 2018 +0200
     1.3 @@ -0,0 +1,6 @@
     1.4 +\.o$
     1.5 +\.d$
     1.6 +\.swp$
     1.7 +\.bin$
     1.8 +\.elf$
     1.9 +\.adf$
     2.1 --- a/Makefile	Wed Feb 21 12:00:13 2018 +0200
     2.2 +++ b/Makefile	Wed Feb 21 18:00:45 2018 +0200
     2.3 @@ -1,5 +1,6 @@
     2.4 +src = $(wildcard src/*.c)
     2.5  asrc = $(wildcard src/*.s)
     2.6 -obj = $(asrc:.s=.o)
     2.7 +obj = $(src:.c=.o) $(asrc:.s=.o) 
     2.8  
     2.9  name = test
    2.10  elf = $(name).elf
    2.11 @@ -15,6 +16,7 @@
    2.12  OBJCOPY = $(tool_prefix)objcopy
    2.13  
    2.14  ASFLAGS = -m68000
    2.15 +CFLAGS = -m68000 -pedantic -Wall
    2.16  LDFLAGS = -T amiga.ld -print-gc-sections \
    2.17  		  -L/usr/lib/gcc-cross/m68k-linux-gnu/6 -lgcc
    2.18  
     3.1 --- a/amiga.ld	Wed Feb 21 12:00:13 2018 +0200
     3.2 +++ b/amiga.ld	Wed Feb 21 18:00:45 2018 +0200
     3.3 @@ -1,27 +1,27 @@
     3.4  OUTPUT_ARCH(m68k)
     3.5  
     3.6 -MEMORY
     3.7 -{
     3.8 -	chipram : ORIGIN = 0, LENGTH = 0x80000
     3.9 -}
    3.10 -
    3.11  PROVIDE (_stacktop = 0x80000);
    3.12  
    3.13  SECTIONS {
    3.14  	/* bootblock will load us at 100h, after the interrupt vectors */
    3.15  	. = 0x100;
    3.16  
    3.17 -	.text : { * (.text); } >chipram
    3.18 -	.rodata : { * (.rodata); } >chipram
    3.19 -	.data : { * (.data); } >chipram
    3.20 +	.text : {
    3.21 +		* (.text.startup);
    3.22 +		* (.text);
    3.23 +	}
    3.24 +	.rodata : { * (.rodata); }
    3.25 +	.data : { * (.data); }
    3.26 +
    3.27 +	.dummy ALIGN(4): { LONG(42); }
    3.28  
    3.29  	.bss ALIGN(4): {
    3.30  		_bss_start = .;
    3.31  		* (.bss);
    3.32  		. = ALIGN(4);
    3.33  		_bss_end = .;
    3.34 -	} >chipram
    3.35 +	}
    3.36  	_bss_size = SIZEOF(.bss);
    3.37  
    3.38 -	.dummy ALIGN(4): { LONG(42); } >chipram
    3.39 +	_mem_start = .;
    3.40  }
     4.1 --- a/src/boot/boot.s	Wed Feb 21 12:00:13 2018 +0200
     4.2 +++ b/src/boot/boot.s	Wed Feb 21 18:00:45 2018 +0200
     4.3 @@ -1,24 +1,20 @@
     4.4  | vi:filetype=gas68k:
     4.5 -
     4.6  	.equ CMD_READ, 2
     4.7  
     4.8  	.equ EXEC_DO_IO, -0x1c8
     4.9  
    4.10  | starting with trackdisk device I/O request pointer in a1
    4.11 -| load the program at 0x100 and return with that value in a0
    4.12 -| program length is patched by mk_adf at start - 4
    4.13 +| load the program at 0x100 and jump there
    4.14 +| program length is patched by mk_adf just before start
    4.15  start:
    4.16 +	move.l -6(%pc), %d0		| get binary size
    4.17 +	move.l %d0, 0x24(%a1)		| I/O length
    4.18  	move.l #0x100, 0x28(%a1)	| I/O data pointer
    4.19 -	move.l start - 4, 0x24(%a1)	| I/O length (1 sector for now)
    4.20  	move.l #512, 0x2c(%a1)		| I/O offset (skip first sector)
    4.21  	move.w #CMD_READ, 0x1c(%a1)	| I/O command
    4.22  	move.l %a1, -(%sp)
    4.23  	jsr EXEC_DO_IO(%a6)
    4.24  	move.l (%sp)+, %a1
    4.25 -	move.b 0x1f(%a1), %d0
    4.26  
    4.27 -	move.l #0x100, %a0
    4.28 -	rts
    4.29 -
    4.30 -	.ascii "bootblock_end"
    4.31 +	bra 0x100
    4.32  	.align 4
     5.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     5.2 +++ b/src/copper.c	Wed Feb 21 18:00:45 2018 +0200
     5.3 @@ -0,0 +1,77 @@
     5.4 +#include "copper.h"
     5.5 +#include "hwregs.h"
     5.6 +
     5.7 +uint32_t *copperlist, *copperlist_end;
     5.8 +static uint32_t *copmem, *curlist;
     5.9 +static int mode, copmem_size;
    5.10 +
    5.11 +extern uint32_t _mem_start;
    5.12 +
    5.13 +int init_copper(int maxlist, int nlists)
    5.14 +{
    5.15 +	/* allocate and set new copper lists */
    5.16 +	if(maxlist <= 0) maxlist = 256;
    5.17 +	mode = nlists >= COPPER_DOUBLE ? COPPER_DOUBLE : COPPER_SINGLE;
    5.18 +
    5.19 +	copmem_size = maxlist * 4 * mode;
    5.20 +	copmem = (uint32_t*)_mem_start;
    5.21 +
    5.22 +	curlist = copperlist = copmem;
    5.23 +	*curlist = COPPER_END;
    5.24 +
    5.25 +	if(mode == COPPER_DOUBLE) {
    5.26 +		copperlist = curlist + maxlist;
    5.27 +		*copperlist = COPPER_END;
    5.28 +	}
    5.29 +	copperlist_end = copperlist;
    5.30 +
    5.31 +	REG32_COP1LC = (uint32_t)curlist;
    5.32 +	REG_COPJMP1 = 0;	/* causes copper to read COP1LC */
    5.33 +	return 0;
    5.34 +}
    5.35 +
    5.36 +void cleanup_copper(void)
    5.37 +{
    5.38 +}
    5.39 +
    5.40 +void enable_copper(void)
    5.41 +{
    5.42 +	REG_DMACON = SETBITS(DMA_COPPER);
    5.43 +}
    5.44 +
    5.45 +void disable_copper(void)
    5.46 +{
    5.47 +	REG_DMACON = CLRBITS(DMA_COPPER);
    5.48 +}
    5.49 +
    5.50 +void clear_copper(void)
    5.51 +{
    5.52 +	copperlist_end = copperlist;
    5.53 +	*copperlist_end = COPPER_END;
    5.54 +}
    5.55 +
    5.56 +void add_copper(uint32_t cmd)
    5.57 +{
    5.58 +	*copperlist_end++ = cmd;
    5.59 +}
    5.60 +
    5.61 +void sort_copper(void)
    5.62 +{
    5.63 +	/* TODO */
    5.64 +}
    5.65 +
    5.66 +void swap_copper(void)
    5.67 +{
    5.68 +	if(mode == COPPER_DOUBLE) {
    5.69 +		uint32_t *tmpptr;
    5.70 +		tmpptr = curlist;
    5.71 +		curlist = copperlist;
    5.72 +		copperlist = copperlist_end = tmpptr;
    5.73 +
    5.74 +		REG32_COP1LC = (uint32_t)curlist;
    5.75 +		REG_COPJMP1 = 0;
    5.76 +	} else {
    5.77 +		copperlist_end = curlist;
    5.78 +	}
    5.79 +	*copperlist_end = COPPER_END;
    5.80 +}
     6.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     6.2 +++ b/src/copper.h	Wed Feb 21 18:00:45 2018 +0200
     6.3 @@ -0,0 +1,38 @@
     6.4 +#ifndef COPPER_H_
     6.5 +#define COPPER_H_
     6.6 +
     6.7 +#include "inttypes.h"
     6.8 +
     6.9 +#define COPPER_MOVE(reg, data)	(((uint32_t)(reg) << 16) | ((uint32_t)(data) & 0xffff))
    6.10 +#define COPPER_WAIT(x, y) \
    6.11 +	(0x0001fffe | ((uint32_t)((x) + 0x81) << 16) | ((uint32_t)((y) + 0x2c) << 24))
    6.12 +#define COPPER_WAIT_OVERSCAN(x, y) \
    6.13 +	(0x0001fffe | ((uint32_t)(x) << 16) | ((uint32_t)(y) << 24))
    6.14 +#define COPPER_VWAIT(s)			(0x0001ff00 | ((uint32_t)((s) + 0x2c) << 24))
    6.15 +#define COPPER_VWAIT_OVERSCAN(s) \
    6.16 +	(0x0001ff00 | ((uint32_t)(s) << 24))
    6.17 +#define COPPER_END				0xfffffffe
    6.18 +
    6.19 +extern uint32_t *copperlist, *copperlist_end;
    6.20 +
    6.21 +enum {
    6.22 +	COPPER_SINGLE = 1,
    6.23 +	COPPER_DOUBLE = 2
    6.24 +};
    6.25 +
    6.26 +int init_copper(int maxlist, int nlists);
    6.27 +void cleanup_copper(void);
    6.28 +
    6.29 +/* enables copper DMA */
    6.30 +void enable_copper(void);
    6.31 +/* disables copper DMA */
    6.32 +void disable_copper(void);
    6.33 +
    6.34 +void clear_copper(void);
    6.35 +void add_copper(uint32_t cmd);
    6.36 +void sort_copper(void);	/* TODO */
    6.37 +
    6.38 +void swap_copper(void);
    6.39 +
    6.40 +
    6.41 +#endif	/* COPPER_H_ */
     7.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     7.2 +++ b/src/hwregs.h	Wed Feb 21 18:00:45 2018 +0200
     7.3 @@ -0,0 +1,428 @@
     7.4 +#ifndef HWREGS_H_
     7.5 +#define HWREGS_H_
     7.6 +
     7.7 +#include "inttypes.h"
     7.8 +
     7.9 +#define REG_BASE_ADDR	0xdff000
    7.10 +
    7.11 +#define REGN_BLTDDAT	0x000
    7.12 +#define REGN_DMACONR	0x002
    7.13 +#define REGN_VPOSR		0x004
    7.14 +#define REGN_VHPOSR		0x006
    7.15 +#define REGN_DSKDATR	0x008
    7.16 +#define REGN_JOY0DAT	0x00a
    7.17 +#define REGN_JOY1DAT	0x00c
    7.18 +#define REGN_CLXDAT		0x00e
    7.19 +#define REGN_ADKCONR	0x010
    7.20 +#define REGN_POT0DAT	0x012
    7.21 +#define REGN_POT1DAT	0x014
    7.22 +#define REGN_POTGOR		0x016
    7.23 +#define REGN_SERDATR	0x018
    7.24 +#define REGN_DSKBYTR	0x01a
    7.25 +#define REGN_INTENAR	0x01c
    7.26 +#define REGN_INTREQR	0x01e
    7.27 +#define REGN_DSKPTH		0x020
    7.28 +#define REGN_DSKPTL		0x022
    7.29 +#define REGN_DSKLEN		0x024
    7.30 +#define REGN_DSKDAT		0x026
    7.31 +#define REGN_REFPTR		0x028
    7.32 +#define REGN_VPOSW		0x02a
    7.33 +#define REGN_VHPOSW		0x02c
    7.34 +#define REGN_COPCON		0x02e
    7.35 +#define REGN_SERDAT		0x030
    7.36 +#define REGN_SERPER		0x032
    7.37 +#define REGN_POTGO		0x034
    7.38 +#define REGN_JOYTEST	0x036
    7.39 +#define REGN_STREQU		0x038
    7.40 +#define REGN_STRVBL		0x03a
    7.41 +#define REGN_STRHOR		0x03c
    7.42 +#define REGN_STRLONG	0x03e
    7.43 +#define REGN_BLTCON0	0x040
    7.44 +#define REGN_BLTCON1	0x042
    7.45 +#define REGN_BLTAFWM	0x044
    7.46 +#define REGN_BLTALWM	0x046
    7.47 +#define REGN_BLTCPTH	0x048
    7.48 +#define REGN_BLTCPTL	0x04a
    7.49 +#define REGN_BLTBPTH	0x04c
    7.50 +#define REGN_BLTBPTL	0x04e
    7.51 +#define REGN_BLTAPTH	0x050
    7.52 +#define REGN_BLTAPTL	0x052
    7.53 +#define REGN_BLTDPTH	0x054
    7.54 +#define REGN_BLTDPTL	0x056
    7.55 +#define REGN_BLTSIZE	0x058
    7.56 +#define REGN_BLTCON0L	0x05a
    7.57 +#define REGN_BLTSIZV	0x05c
    7.58 +#define REGN_BLTSIZH	0x05e
    7.59 +#define REGN_BLTCMOD	0x060
    7.60 +#define REGN_BLTBMOD	0x062
    7.61 +#define REGN_BLTAMOD	0x064
    7.62 +#define REGN_BLTDMOD	0x066
    7.63 +#define REGN_BLTCDAT	0x070
    7.64 +#define REGN_BLTBDAT	0x072
    7.65 +#define REGN_BLTADAT	0x074
    7.66 +#define REGN_SPRHDAT	0x078
    7.67 +#define REGN_DENISEID	0x07c
    7.68 +#define REGN_DSKSYNC	0x07e
    7.69 +#define REGN_COP1LCH	0x080
    7.70 +#define REGN_COP1LCL	0x082
    7.71 +#define REGN_COP2LCH	0x084
    7.72 +#define REGN_COP2LCL	0x086
    7.73 +#define REGN_CMPJMP1	0x088
    7.74 +#define REGN_CMPJMP2	0x08a
    7.75 +#define REGN_COPINS		0x08c
    7.76 +#define REGN_DIWSTART	0x08e
    7.77 +#define REGN_DIWSTOP	0x090
    7.78 +#define REGN_DDFSTART	0x092
    7.79 +#define REGN_DDFSTOP	0x094
    7.80 +#define REGN_DMACON		0x096
    7.81 +#define REGN_CLXCON		0x098
    7.82 +#define REGN_INTENA		0x09a
    7.83 +#define REGN_INTREQ		0x09c
    7.84 +#define REGN_ADKCON		0x09e
    7.85 +
    7.86 +#define REGN_AUDIO_LCH(c)	(REGN_AUDIO0_BASE + (c) * 16 + 0)
    7.87 +#define REGN_AUDIO_LCL(c)	(REGN_AUDIO0_BASE + (c) * 16 + 2)
    7.88 +#define REGN_AUDIO_LEN(c)	(REGN_AUDIO0_BASE + (c) * 16 + 4)
    7.89 +#define REGN_AUDIO_PER(c)	(REGN_AUDIO0_BASE + (c) * 16 + 6)
    7.90 +#define REGN_AUDIO_VOL(c)	(REGN_AUDIO0_BASE + (c) * 16 + 8)
    7.91 +#define REGN_AUDIO_DAT(c)	(REGN_AUDIO0_BASE + (c) * 16 + 10)
    7.92 +
    7.93 +#define REGN_AUDIO0_BASE	0x0a0
    7.94 +#define REGN_AUD0LCH		(REGN_AUDIO0_BASE + 0)
    7.95 +#define REGN_AUD0LCL		(REGN_AUDIO0_BASE + 2)
    7.96 +#define REGN_AUD0LEN		(REGN_AUDIO0_BASE + 4)
    7.97 +#define REGN_AUD0PER		(REGN_AUDIO0_BASE + 6)
    7.98 +#define REGN_AUD0VOL		(REGN_AUDIO0_BASE + 8)
    7.99 +#define REGN_AUD0DAT		(REGN_AUDIO0_BASE + 10)
   7.100 +#define REGN_AUDIO1_BASE	0x0b0
   7.101 +#define REGN_AUD1LCH		(REGN_AUDIO1_BASE + 0)
   7.102 +#define REGN_AUD1LCL		(REGN_AUDIO1_BASE + 2)
   7.103 +#define REGN_AUD1LEN		(REGN_AUDIO1_BASE + 4)
   7.104 +#define REGN_AUD1PER		(REGN_AUDIO1_BASE + 6)
   7.105 +#define REGN_AUD1VOL		(REGN_AUDIO1_BASE + 8)
   7.106 +#define REGN_AUD1DAT		(REGN_AUDIO1_BASE + 10)
   7.107 +#define REGN_AUDIO2_BASE	0x0c0
   7.108 +#define REGN_AUD2LCH		(REGN_AUDIO2_BASE + 0)
   7.109 +#define REGN_AUD2LCL		(REGN_AUDIO2_BASE + 2)
   7.110 +#define REGN_AUD2LEN		(REGN_AUDIO2_BASE + 4)
   7.111 +#define REGN_AUD2PER		(REGN_AUDIO2_BASE + 6)
   7.112 +#define REGN_AUD2VOL		(REGN_AUDIO2_BASE + 8)
   7.113 +#define REGN_AUD2DAT		(REGN_AUDIO2_BASE + 10)
   7.114 +#define REGN_AUDIO3_BASE	0x0d0
   7.115 +#define REGN_AUD3LCH		(REGN_AUDIO3_BASE + 0)
   7.116 +#define REGN_AUD3LCL		(REGN_AUDIO3_BASE + 2)
   7.117 +#define REGN_AUD3LEN		(REGN_AUDIO3_BASE + 4)
   7.118 +#define REGN_AUD3PER		(REGN_AUDIO3_BASE + 6)
   7.119 +#define REGN_AUD3VOL		(REGN_AUDIO3_BASE + 8)
   7.120 +#define REGN_AUD3DAT		(REGN_AUDIO3_BASE + 10)
   7.121 +
   7.122 +#define REGN_BPL1PTH	0x0e0
   7.123 +#define REGN_BPL1PTL	0x0e2
   7.124 +#define REGN_BPL2PTH	0x0e4
   7.125 +#define REGN_BPL2PTL	0x0e6
   7.126 +#define REGN_BPL3PTH	0x0e8
   7.127 +#define REGN_BPL3PTL	0x0ea
   7.128 +#define REGN_BPL4PTH	0x0ec
   7.129 +#define REGN_BPL4PTL	0x0ee
   7.130 +#define REGN_BPL5PTH	0x0f0
   7.131 +#define REGN_BPL5PTL	0x0f2
   7.132 +#define REGN_BPL6PTH	0x0f4
   7.133 +#define REGN_BPL6PTL	0x0f6
   7.134 +#define REGN_BPLCON0	0x100
   7.135 +#define REGN_BPLCON1	0x102
   7.136 +#define REGN_BPLCON2	0x104
   7.137 +#define REGN_BPLCON3	0x106
   7.138 +#define REGN_BPL1MOD	0x108
   7.139 +#define REGN_BPL2MOD	0x10a
   7.140 +#define REGN_BPL1DAT	0x110
   7.141 +#define REGN_BPL2DAT	0x112
   7.142 +#define REGN_BPL3DAT	0x114
   7.143 +#define REGN_BPL4DAT	0x116
   7.144 +#define REGN_BPL5DAT	0x118
   7.145 +#define REGN_BPL6DAT	0x11a
   7.146 +
   7.147 +#define REGN_SPR0PTH	0x120
   7.148 +#define REGN_SPR0PTL	0x122
   7.149 +#define REGN_SPR1PTH	0x124
   7.150 +#define REGN_SPR1PTL	0x126
   7.151 +#define REGN_SPR2PTH	0x128
   7.152 +#define REGN_SPR2PTL	0x12a
   7.153 +#define REGN_SPR3PTH	0x12c
   7.154 +#define REGN_SPR3PTL	0x12e
   7.155 +#define REGN_SPR4PTH	0x130
   7.156 +#define REGN_SPR4PTL	0x132
   7.157 +#define REGN_SPR5PTH	0x134
   7.158 +#define REGN_SPR5PTL	0x136
   7.159 +#define REGN_SPR6PTH	0x138
   7.160 +#define REGN_SPR6PTL	0x13a
   7.161 +#define REGN_SPR7PTH	0x13c
   7.162 +#define REGN_SPR7PTL	0x13e
   7.163 +
   7.164 +#define REGN_SPRITE_POS(s)	(REGN_SPRITE0_BASE + (s) * 8 + 0)
   7.165 +#define REGN_SPRITE_CTL(s)	(REGN_SPRITE0_BASE + (s) * 8 + 2)
   7.166 +#define REGN_SPRITE_DATA(s)	(REGN_SPRITE0_BASE + (s) * 8 + 4)
   7.167 +#define REGN_SPRITE_DATB(s)	(REGN_SPRITE0_BASE + (s) * 8 + 6)
   7.168 +
   7.169 +#define REGN_SPRITE0_BASE	0x140
   7.170 +#define REGN_SPR0POS		REGN_SPRITE_POS(0)
   7.171 +#define REGN_SPR0CTL		REGN_SPRITE_CTL(0)
   7.172 +#define REGN_SPR0DATA		REGN_SPRITE_DATA(0)
   7.173 +#define REGN_SPR0DATB		REGN_SPRITE_DATB(0)
   7.174 +#define REGN_SPRITE1_BASE	0x148
   7.175 +#define REGN_SPR1POS		REGN_SPRITE_POS(1)
   7.176 +#define REGN_SPR1CTL		REGN_SPRITE_CTL(1)
   7.177 +#define REGN_SPR1DATA		REGN_SPRITE_DATA(1)
   7.178 +#define REGN_SPR1DATB		REGN_SPRITE_DATB(1)
   7.179 +#define REGN_SPRITE2_BASE	0x150
   7.180 +#define REGN_SPR2POS		REGN_SPRITE_POS(2)
   7.181 +#define REGN_SPR2CTL		REGN_SPRITE_CTL(2)
   7.182 +#define REGN_SPR2DATA		REGN_SPRITE_DATA(2)
   7.183 +#define REGN_SPR2DATB		REGN_SPRITE_DATB(2)
   7.184 +#define REGN_SPRITE3_BASE	0x158
   7.185 +#define REGN_SPR3POS		REGN_SPRITE_POS(3)
   7.186 +#define REGN_SPR3CTL		REGN_SPRITE_CTL(3)
   7.187 +#define REGN_SPR3DATA		REGN_SPRITE_DATA(3)
   7.188 +#define REGN_SPR3DATB		REGN_SPRITE_DATB(3)
   7.189 +#define REGN_SPRITE4_BASE	0x160
   7.190 +#define REGN_SPR4POS		REGN_SPRITE_POS(4)
   7.191 +#define REGN_SPR4CTL		REGN_SPRITE_CTL(4)
   7.192 +#define REGN_SPR4DATA		REGN_SPRITE_DATA(4)
   7.193 +#define REGN_SPR4DATB		REGN_SPRITE_DATB(4)
   7.194 +#define REGN_SPRITE5_BASE	0x168
   7.195 +#define REGN_SPR5POS		REGN_SPRITE_POS(5)
   7.196 +#define REGN_SPR5CTL		REGN_SPRITE_CTL(5)
   7.197 +#define REGN_SPR5DATA		REGN_SPRITE_DATA(5)
   7.198 +#define REGN_SPR5DATB		REGN_SPRITE_DATB(5)
   7.199 +#define REGN_SPRITE6_BASE	0x170
   7.200 +#define REGN_SPR6POS		REGN_SPRITE_POS(6)
   7.201 +#define REGN_SPR6CTL		REGN_SPRITE_CTL(6)
   7.202 +#define REGN_SPR6DATA		REGN_SPRITE_DATA(6)
   7.203 +#define REGN_SPR6DATB		REGN_SPRITE_DATB(6)
   7.204 +#define REGN_SPRITE7_BASE	0x178
   7.205 +#define REGN_SPR7POS		REGN_SPRITE_POS(7)
   7.206 +#define REGN_SPR7CTL		REGN_SPRITE_CTL(7)
   7.207 +#define REGN_SPR7DATA		REGN_SPRITE_DATA(7)
   7.208 +#define REGN_SPR7DATB		REGN_SPRITE_DATB(7)
   7.209 +
   7.210 +#define REGN_COLOR_BASE		0x180
   7.211 +#define REGN_COLOR(idx)		(REGN_COLOR_BASE + (idx) * 2)
   7.212 +
   7.213 +#define REGN_COLOR0			REGN_COLOR(0)
   7.214 +#define REGN_COLOR1			REGN_COLOR(1)
   7.215 +#define REGN_COLOR2			REGN_COLOR(2)
   7.216 +#define REGN_COLOR3			REGN_COLOR(3)
   7.217 +#define REGN_COLOR4			REGN_COLOR(4)
   7.218 +#define REGN_COLOR5			REGN_COLOR(5)
   7.219 +#define REGN_COLOR6			REGN_COLOR(6)
   7.220 +#define REGN_COLOR7			REGN_COLOR(7)
   7.221 +#define REGN_COLOR8			REGN_COLOR(8)
   7.222 +#define REGN_COLOR9			REGN_COLOR(9)
   7.223 +#define REGN_COLOR10		REGN_COLOR(10)
   7.224 +#define REGN_COLOR11		REGN_COLOR(11)
   7.225 +#define REGN_COLOR12		REGN_COLOR(12)
   7.226 +#define REGN_COLOR13		REGN_COLOR(13)
   7.227 +#define REGN_COLOR14		REGN_COLOR(14)
   7.228 +#define REGN_COLOR15		REGN_COLOR(15)
   7.229 +#define REGN_COLOR16		REGN_COLOR(16)
   7.230 +#define REGN_COLOR17		REGN_COLOR(17)
   7.231 +#define REGN_COLOR18		REGN_COLOR(18)
   7.232 +#define REGN_COLOR19		REGN_COLOR(19)
   7.233 +#define REGN_COLOR20		REGN_COLOR(20)
   7.234 +#define REGN_COLOR21		REGN_COLOR(21)
   7.235 +#define REGN_COLOR22		REGN_COLOR(22)
   7.236 +#define REGN_COLOR23		REGN_COLOR(23)
   7.237 +#define REGN_COLOR24		REGN_COLOR(24)
   7.238 +#define REGN_COLOR25		REGN_COLOR(25)
   7.239 +#define REGN_COLOR26		REGN_COLOR(26)
   7.240 +#define REGN_COLOR27		REGN_COLOR(27)
   7.241 +#define REGN_COLOR28		REGN_COLOR(28)
   7.242 +#define REGN_COLOR29		REGN_COLOR(29)
   7.243 +#define REGN_COLOR30		REGN_COLOR(30)
   7.244 +#define REGN_COLOR31		REGN_COLOR(31)
   7.245 +
   7.246 +#define REGN_HTOTAL		0x1c0
   7.247 +#define REGN_HSSTOP		0x1c2
   7.248 +#define REGN_HBSTART	0x1c4
   7.249 +#define REGN_HBSTOP		0x1c6
   7.250 +#define REGN_VTOTAL		0x1c8
   7.251 +#define REGN_VSSTOP		0x1ca
   7.252 +#define REGN_VBSTART	0x1cc
   7.253 +#define REGN_VBSTOP		0x1ce
   7.254 +#define REGN_BEAMCON0	0x1dc
   7.255 +#define REGN_HSSTART	0x1de
   7.256 +#define REGN_VSSTART	0x1e0
   7.257 +#define REGN_HCENTER	0x1e2
   7.258 +#define REGN_DIWHIGH	0x1e4
   7.259 +
   7.260 +#define REGN_COP1LCH	0x080
   7.261 +#define REGN_COP1LCL	0x082
   7.262 +#define REGN_COP2LCH	0x084
   7.263 +#define REGN_COP2LCL	0x086
   7.264 +#define REGN_COPJMP1	0x088
   7.265 +#define REGN_COPJMP2	0x08a
   7.266 +
   7.267 +#define REG(r)	(*(volatile uint16_t*)(REG_BASE_ADDR | (r)))
   7.268 +
   7.269 +#define REG_CIAA_PORTA	*(volatile uint8_t*)0xbfe001
   7.270 +
   7.271 +#define REG_INTENA		REG(REGN_INTENA)
   7.272 +#define REG_INTENAR		REG(REGN_INTENAR)
   7.273 +#define REG_INTREQ		REG(REGN_INTREQ)
   7.274 +#define REG_INTREQR		REG(REGN_INTREQR)
   7.275 +#define REG_ADKCON		REG(REGN_ADKCON)
   7.276 +#define REG_ADKCONR		REG(REGN_ADKCONR)
   7.277 +#define REG_DMACON		REG(REGN_DMACON)
   7.278 +#define REG_DMACONR		REG(REGN_DMACONR)
   7.279 +#define REG_BPLCON0		REG(REGN_BPLCON0)
   7.280 +#define REG_BPLCON1		REG(REGN_BPLCON1)
   7.281 +#define REG_BPLCON2		REG(REGN_BPLCON2)
   7.282 +#define REG_BPL1PTH		REG(REGN_BPL1PTH)
   7.283 +#define REG_BPL2PTH		REG(REGN_BPL2PTH)
   7.284 +#define REG_BPL3PTH		REG(REGN_BPL3PTH)
   7.285 +#define REG_BPL4PTH		REG(REGN_BPL4PTH)
   7.286 +#define REG_BPL5PTH		REG(REGN_BPL5PTH)
   7.287 +#define REG_BPL6PTH		REG(REGN_BPL6PTH)
   7.288 +#define REG_BPL1PTL		REG(REGN_BPL1PTL)
   7.289 +#define REG_BPL2PTL		REG(REGN_BPL2PTL)
   7.290 +#define REG_BPL3PTL		REG(REGN_BPL3PTL)
   7.291 +#define REG_BPL4PTL		REG(REGN_BPL4PTL)
   7.292 +#define REG_BPL5PTL		REG(REGN_BPL5PTL)
   7.293 +#define REG_BPL6PTL		REG(REGN_BPL6PTL)
   7.294 +#define REG32_BPL1PT	*(volatile uint32_t*)(REG_BASE_ADDR | REGN_BPL1PTH)
   7.295 +#define REG32_BPL2PT	*(volatile uint32_t*)(REG_BASE_ADDR | REGN_BPL2PTH)
   7.296 +#define REG32_BPL3PT	*(volatile uint32_t*)(REG_BASE_ADDR | REGN_BPL3PTH)
   7.297 +#define REG32_BPL4PT	*(volatile uint32_t*)(REG_BASE_ADDR | REGN_BPL4PTH)
   7.298 +#define REG32_BPL5PT	*(volatile uint32_t*)(REG_BASE_ADDR | REGN_BPL5PTH)
   7.299 +#define REG32_BPL6PT	*(volatile uint32_t*)(REG_BASE_ADDR | REGN_BPL6PTH)
   7.300 +#define REG_BPL1MOD		REG(REGN_BPL1MOD)
   7.301 +#define REG_BPL2MOD		REG(REGN_BPL2MOD)
   7.302 +#define REG_DIWSTART	REG(REGN_DIWSTART)
   7.303 +#define REG_DIWSTOP		REG(REGN_DIWSTOP)
   7.304 +#define REG_DDFSTART	REG(REGN_DDFSTART)
   7.305 +#define REG_DDFSTOP		REG(REGN_DDFSTOP)
   7.306 +#define REG_VPOS		REG(REGN_VPOS)
   7.307 +#define REG_VPOSR		REG(REGN_VPOSR)
   7.308 +#define REG_VHPOS		REG(REGN_VHPOS)
   7.309 +#define REG_VHPOSR		REG(REGN_VHPOSR)
   7.310 +#define REG32_VPOSR		*(volatile uint32_t*)(REG_BASE_ADDR | REGN_VPOSR)
   7.311 +
   7.312 +#define REG_COLOR_PTR	((volatile uint16_t*)(REG_BASE_ADDR | REGN_COLOR0))
   7.313 +#define REG_COLOR0		REG(REGN_COLOR0)
   7.314 +#define REG_COLOR1		REG(REGN_COLOR1)
   7.315 +#define REG_COLOR2		REG(REGN_COLOR2)
   7.316 +#define REG_COLOR3		REG(REGN_COLOR3)
   7.317 +#define REG_COLOR4		REG(REGN_COLOR4)
   7.318 +#define REG_COLOR5		REG(REGN_COLOR5)
   7.319 +#define REG_COLOR6		REG(REGN_COLOR6)
   7.320 +#define REG_COLOR7		REG(REGN_COLOR7)
   7.321 +#define REG_COLOR8		REG(REGN_COLOR8)
   7.322 +#define REG_COLOR9		REG(REGN_COLOR9)
   7.323 +#define REG_COLOR10		REG(REGN_COLOR10)
   7.324 +#define REG_COLOR11		REG(REGN_COLOR11)
   7.325 +#define REG_COLOR12		REG(REGN_COLOR12)
   7.326 +#define REG_COLOR13		REG(REGN_COLOR13)
   7.327 +#define REG_COLOR14		REG(REGN_COLOR14)
   7.328 +#define REG_COLOR15		REG(REGN_COLOR15)
   7.329 +#define REG_COLOR16		REG(REGN_COLOR16)
   7.330 +#define REG_COLOR17		REG(REGN_COLOR17)
   7.331 +#define REG_COLOR18		REG(REGN_COLOR18)
   7.332 +#define REG_COLOR19		REG(REGN_COLOR19)
   7.333 +#define REG_COLOR20		REG(REGN_COLOR20)
   7.334 +#define REG_COLOR21		REG(REGN_COLOR21)
   7.335 +#define REG_COLOR22		REG(REGN_COLOR22)
   7.336 +#define REG_COLOR23		REG(REGN_COLOR23)
   7.337 +#define REG_COLOR24		REG(REGN_COLOR24)
   7.338 +#define REG_COLOR25		REG(REGN_COLOR25)
   7.339 +#define REG_COLOR26		REG(REGN_COLOR26)
   7.340 +#define REG_COLOR27		REG(REGN_COLOR27)
   7.341 +#define REG_COLOR28		REG(REGN_COLOR28)
   7.342 +#define REG_COLOR29		REG(REGN_COLOR29)
   7.343 +#define REG_COLOR30		REG(REGN_COLOR30)
   7.344 +#define REG_COLOR31		REG(REGN_COLOR31)
   7.345 +
   7.346 +#define REG32_COP1LC	*(volatile uint32_t*)(REG_BASE_ADDR | REGN_COP1LCH)
   7.347 +#define REG32_COP2LC	*(volatile uint32_t*)(REG_BASE_ADDR | REGN_COP2LCH)
   7.348 +#define REG_COPJMP1		REG(REGN_COPJMP1)
   7.349 +#define REG_COPJMP2		REG(REGN_COPJMP2)
   7.350 +
   7.351 +/* ------ bits ------- */
   7.352 +#define SETBITS(x)	((x) | 0x8000)
   7.353 +#define CLRBITS(x)	(x)
   7.354 +
   7.355 +/* interrupt numbers */
   7.356 +enum {
   7.357 +	INTR_TBE,
   7.358 +	INTR_DSKBLK,
   7.359 +	INTR_SOFT,
   7.360 +	INTR_PORTS,
   7.361 +	INTR_COPPER,
   7.362 +	INTR_VERTB,
   7.363 +	INTR_BLITTER,
   7.364 +	INTR_AUDIO0,
   7.365 +	INTR_AUDIO1,
   7.366 +	INTR_AUDIO2,
   7.367 +	INTR_AUDIO3,
   7.368 +	INTR_RBF,
   7.369 +	INTR_DSKSYN,
   7.370 +	INTR_EXTER
   7.371 +};
   7.372 +
   7.373 +/* interrupt enable flags */
   7.374 +enum {
   7.375 +	INTEN_TBE		= 0x0001,
   7.376 +	INTEN_DSKBLK	= 0x0002,
   7.377 +	INTEN_SOFT		= 0x0004,
   7.378 +	INTEN_PORTS		= 0x0008,
   7.379 +	INTEN_COPPER	= 0x0010,
   7.380 +	INTEN_VERTB		= 0x0020,
   7.381 +	INTEN_BLITTER	= 0x0040,
   7.382 +	INTEN_AUDIO0	= 0x0080,
   7.383 +	INTEN_AUDIO1	= 0x0100,
   7.384 +	INTEN_AUDIO2	= 0x0200,
   7.385 +	INTEN_AUDIO3	= 0x0400,
   7.386 +	INTEN_RBF		= 0x0800,
   7.387 +	INTEN_DSKSYN	= 0x1000,
   7.388 +	INTEN_EXTER		= 0x2000,
   7.389 +	INTEN_MASTER	= 0x4000,
   7.390 +
   7.391 +	INTEN_ALL		= 0x7fff
   7.392 +};
   7.393 +
   7.394 +/* DMA control flags */
   7.395 +enum {
   7.396 +	DMA_AUD0		= 0x0001,
   7.397 +	DMA_AUD1		= 0x0002,
   7.398 +	DMA_AUD2		= 0x0004,
   7.399 +	DMA_AUD3		= 0x0008,
   7.400 +	DMA_AUDIO		= 0x000f,	/* all the above */
   7.401 +	DMA_DISK		= 0x0010,
   7.402 +	DMA_SPRITE		= 0x0020,
   7.403 +	DMA_BLITTER		= 0x0040,
   7.404 +	DMA_COPPER		= 0x0080,
   7.405 +	DMA_BPL			= 0x0100,
   7.406 +	DMA_MASTER		= 0x0200,
   7.407 +
   7.408 +	DMA_ALL			= 0x01ff
   7.409 +};
   7.410 +
   7.411 +/* Bitplane control */
   7.412 +enum {
   7.413 +	BPLCON0_ERSY	= 0x0002,
   7.414 +	BPLCON0_LACE	= 0x0004,
   7.415 +	BPLCON0_LPEN	= 0x0008,
   7.416 +	BPLCON0_GAUD	= 0x0100,
   7.417 +	BPLCON0_COLOR	= 0x0200,
   7.418 +	BPLCON0_DBLPF	= 0x0400,
   7.419 +	BPLCON0_HOMOD	= 0x0800,
   7.420 +	BPLCON0_BPU0	= 0x1000,
   7.421 +	BPLCON0_BPU1	= 0x2000,
   7.422 +	BPLCON0_BPU2	= 0x4000,
   7.423 +	BPLCON0_HIRES	= 0x8000
   7.424 +};
   7.425 +
   7.426 +#define BPLCON0_COUNT(x)	((x) << 12)
   7.427 +
   7.428 +#define CIAA_PA_FIR0	0x40
   7.429 +#define CIAA_PA_FIR1	0x80
   7.430 +
   7.431 +#endif	/* HWREGS_H_ */
     8.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     8.2 +++ b/src/intr.h	Wed Feb 21 18:00:45 2018 +0200
     8.3 @@ -0,0 +1,7 @@
     8.4 +#ifndef INTR_H_
     8.5 +#define INTR_H_
     8.6 +
     8.7 +#define enable_intr() asm volatile ("andi.w #0xf8ff, %sr")
     8.8 +#define disable_intr() asm volatile ("ori.w #0x0300, %sr")
     8.9 +
    8.10 +#endif	/* INTR_H_ */
     9.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     9.2 +++ b/src/intr.s	Wed Feb 21 18:00:45 2018 +0200
     9.3 @@ -0,0 +1,13 @@
     9.4 +	.text
     9.5 +
     9.6 +	.global intr_debug
     9.7 +intr_debug:
     9.8 +	movem.l %d0-%a6, -(%sp)
     9.9 +	move.w dbgval, %d0
    9.10 +	move.w %d0, 0xdff180
    9.11 +	not.w %d0
    9.12 +	move.w %d0, dbgval
    9.13 +	movem.l (%sp)+, %d0-%a6
    9.14 +	rte
    9.15 +
    9.16 +dbgval: .word 0x00f
    10.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    10.2 +++ b/src/inttypes.h	Wed Feb 21 18:00:45 2018 +0200
    10.3 @@ -0,0 +1,11 @@
    10.4 +#ifndef INTTYPES_H_
    10.5 +#define INTTYPES_H_
    10.6 +
    10.7 +typedef signed char int8_t;
    10.8 +typedef unsigned char uint8_t;
    10.9 +typedef short int16_t;
   10.10 +typedef unsigned short uint16_t;
   10.11 +typedef long int32_t;
   10.12 +typedef unsigned long uint32_t;
   10.13 +
   10.14 +#endif	/* INTTYPES_H_ */
    11.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    11.2 +++ b/src/main.c	Wed Feb 21 18:00:45 2018 +0200
    11.3 @@ -0,0 +1,59 @@
    11.4 +#include "hwregs.h"
    11.5 +#include "intr.h"
    11.6 +#include "copper.h"
    11.7 +
    11.8 +void wait_vpos(int x);
    11.9 +void wait_vblank(void);
   11.10 +
   11.11 +#define BPLSZ  (320 / 8 * 256)
   11.12 +static unsigned char fb0[BPLSZ];
   11.13 +
   11.14 +int main(void)
   11.15 +{
   11.16 +	uint32_t fb0_addr = (uint32_t)fb0;
   11.17 +
   11.18 +	REG_INTENA = SETBITS(INTEN_VERTB | INTEN_MASTER);
   11.19 +
   11.20 +	REG_DMACON = CLRBITS(DMA_ALL);
   11.21 +	REG_BPLCON0 = BPLCON0_COUNT(0) | BPLCON0_COLOR;
   11.22 +	REG_BPLCON1 = 0;
   11.23 +	REG_DIWSTART = 0x2981;
   11.24 +	REG_DIWSTOP = 0x29c1;
   11.25 +	REG_DDFSTART = 0x38;
   11.26 +	REG_DDFSTOP = 0xd0;
   11.27 +
   11.28 +	REG_COLOR0 = 0x00f;
   11.29 +	REG_COLOR1 = 0xff0;
   11.30 +
   11.31 +	init_copper(0, 0);
   11.32 +
   11.33 +	wait_vblank();
   11.34 +	add_copper(COPPER_MOVE(REGN_BPL1PTH, fb0_addr >> 16));
   11.35 +	add_copper(COPPER_MOVE(REGN_BPL1PTL, fb0_addr));
   11.36 +
   11.37 +	add_copper(COPPER_VWAIT(64));
   11.38 +	add_copper(COPPER_MOVE(REGN_COLOR0, 0xf00));
   11.39 +	add_copper(COPPER_VWAIT(70));
   11.40 +	add_copper(COPPER_MOVE(REGN_COLOR0, 0x00f));
   11.41 +
   11.42 +	add_copper(COPPER_END);
   11.43 +
   11.44 +	fb0[128 * 320 / 8] = 8;
   11.45 +
   11.46 +	REG_DMACON = SETBITS(DMA_COPPER | DMA_MASTER);
   11.47 +	enable_intr();
   11.48 +
   11.49 +	for(;;);
   11.50 +	return 0;
   11.51 +}
   11.52 +
   11.53 +void wait_vpos(int x)
   11.54 +{
   11.55 +	x <<= 8;
   11.56 +	while((REG32_VPOSR & 0x1ff00) < x);
   11.57 +}
   11.58 +
   11.59 +void wait_vblank(void)
   11.60 +{
   11.61 +	wait_vpos(300);
   11.62 +}
    12.1 --- a/src/startup.s	Wed Feb 21 12:00:13 2018 +0200
    12.2 +++ b/src/startup.s	Wed Feb 21 18:00:45 2018 +0200
    12.3 @@ -1,12 +1,16 @@
    12.4  | vi:filetype=gas68k:
    12.5 -	.text
    12.6 -
    12.7 -	.equ REG_COL0, 0xdff180
    12.8 -
    12.9  	.global start
   12.10  	.global halt_cpu
   12.11 +	.extern main
   12.12  
   12.13 -start:
   12.14 +	.section .text.startup
   12.15 +
   12.16 +	| enter supervisor mode (assumes VBR=0)
   12.17 +	move.l #super, 0x80
   12.18 +	trap #0
   12.19 +super:
   12.20 +	ori.w #0x0300, %sr	| disable interrupts
   12.21 +
   12.22  	| zero the .bss section
   12.23  	move.l #_bss_start, %a0
   12.24  	move.l #_bss_end, %a1
   12.25 @@ -18,10 +22,10 @@
   12.26  1:
   12.27  	| setup the stack
   12.28  	move.l #_stacktop, %sp
   12.29 +	andi.w #0xf8ff, %sr	| enable interrupts
   12.30  
   12.31 -	| test output
   12.32 -	move.w #0xf0f, REG_COL0
   12.33 -0:	bra.b 0b	| infloop
   12.34 +	jsr main
   12.35 +0:	bra.b 0b
   12.36  
   12.37  halt_cpu:
   12.38  	stop #0x2700