# HG changeset patch # User John Tsiombikas # Date 1519228845 -7200 # Node ID 48093e4bd99addf49529a217191ea9f21032cd74 # Parent 51422ea54b9d0b7d074b9f3dfcd58953eacacc94 stuff diff -r 51422ea54b9d -r 48093e4bd99a .hgignore --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/.hgignore Wed Feb 21 18:00:45 2018 +0200 @@ -0,0 +1,6 @@ +\.o$ +\.d$ +\.swp$ +\.bin$ +\.elf$ +\.adf$ diff -r 51422ea54b9d -r 48093e4bd99a Makefile --- a/Makefile Wed Feb 21 12:00:13 2018 +0200 +++ b/Makefile Wed Feb 21 18:00:45 2018 +0200 @@ -1,5 +1,6 @@ +src = $(wildcard src/*.c) asrc = $(wildcard src/*.s) -obj = $(asrc:.s=.o) +obj = $(src:.c=.o) $(asrc:.s=.o) name = test elf = $(name).elf @@ -15,6 +16,7 @@ OBJCOPY = $(tool_prefix)objcopy ASFLAGS = -m68000 +CFLAGS = -m68000 -pedantic -Wall LDFLAGS = -T amiga.ld -print-gc-sections \ -L/usr/lib/gcc-cross/m68k-linux-gnu/6 -lgcc diff -r 51422ea54b9d -r 48093e4bd99a amiga.ld --- a/amiga.ld Wed Feb 21 12:00:13 2018 +0200 +++ b/amiga.ld Wed Feb 21 18:00:45 2018 +0200 @@ -1,27 +1,27 @@ OUTPUT_ARCH(m68k) -MEMORY -{ - chipram : ORIGIN = 0, LENGTH = 0x80000 -} - PROVIDE (_stacktop = 0x80000); SECTIONS { /* bootblock will load us at 100h, after the interrupt vectors */ . = 0x100; - .text : { * (.text); } >chipram - .rodata : { * (.rodata); } >chipram - .data : { * (.data); } >chipram + .text : { + * (.text.startup); + * (.text); + } + .rodata : { * (.rodata); } + .data : { * (.data); } + + .dummy ALIGN(4): { LONG(42); } .bss ALIGN(4): { _bss_start = .; * (.bss); . = ALIGN(4); _bss_end = .; - } >chipram + } _bss_size = SIZEOF(.bss); - .dummy ALIGN(4): { LONG(42); } >chipram + _mem_start = .; } diff -r 51422ea54b9d -r 48093e4bd99a src/boot/boot.s --- a/src/boot/boot.s Wed Feb 21 12:00:13 2018 +0200 +++ b/src/boot/boot.s Wed Feb 21 18:00:45 2018 +0200 @@ -1,24 +1,20 @@ | vi:filetype=gas68k: - .equ CMD_READ, 2 .equ EXEC_DO_IO, -0x1c8 | starting with trackdisk device I/O request pointer in a1 -| load the program at 0x100 and return with that value in a0 -| program length is patched by mk_adf at start - 4 +| load the program at 0x100 and jump there +| program length is patched by mk_adf just before start start: + move.l -6(%pc), %d0 | get binary size + move.l %d0, 0x24(%a1) | I/O length move.l #0x100, 0x28(%a1) | I/O data pointer - move.l start - 4, 0x24(%a1) | I/O length (1 sector for now) move.l #512, 0x2c(%a1) | I/O offset (skip first sector) move.w #CMD_READ, 0x1c(%a1) | I/O command move.l %a1, -(%sp) jsr EXEC_DO_IO(%a6) move.l (%sp)+, %a1 - move.b 0x1f(%a1), %d0 - move.l #0x100, %a0 - rts - - .ascii "bootblock_end" + bra 0x100 .align 4 diff -r 51422ea54b9d -r 48093e4bd99a src/copper.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/copper.c Wed Feb 21 18:00:45 2018 +0200 @@ -0,0 +1,77 @@ +#include "copper.h" +#include "hwregs.h" + +uint32_t *copperlist, *copperlist_end; +static uint32_t *copmem, *curlist; +static int mode, copmem_size; + +extern uint32_t _mem_start; + +int init_copper(int maxlist, int nlists) +{ + /* allocate and set new copper lists */ + if(maxlist <= 0) maxlist = 256; + mode = nlists >= COPPER_DOUBLE ? COPPER_DOUBLE : COPPER_SINGLE; + + copmem_size = maxlist * 4 * mode; + copmem = (uint32_t*)_mem_start; + + curlist = copperlist = copmem; + *curlist = COPPER_END; + + if(mode == COPPER_DOUBLE) { + copperlist = curlist + maxlist; + *copperlist = COPPER_END; + } + copperlist_end = copperlist; + + REG32_COP1LC = (uint32_t)curlist; + REG_COPJMP1 = 0; /* causes copper to read COP1LC */ + return 0; +} + +void cleanup_copper(void) +{ +} + +void enable_copper(void) +{ + REG_DMACON = SETBITS(DMA_COPPER); +} + +void disable_copper(void) +{ + REG_DMACON = CLRBITS(DMA_COPPER); +} + +void clear_copper(void) +{ + copperlist_end = copperlist; + *copperlist_end = COPPER_END; +} + +void add_copper(uint32_t cmd) +{ + *copperlist_end++ = cmd; +} + +void sort_copper(void) +{ + /* TODO */ +} + +void swap_copper(void) +{ + if(mode == COPPER_DOUBLE) { + uint32_t *tmpptr; + tmpptr = curlist; + curlist = copperlist; + copperlist = copperlist_end = tmpptr; + + REG32_COP1LC = (uint32_t)curlist; + REG_COPJMP1 = 0; + } else { + copperlist_end = curlist; + } + *copperlist_end = COPPER_END; +} diff -r 51422ea54b9d -r 48093e4bd99a src/copper.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/copper.h Wed Feb 21 18:00:45 2018 +0200 @@ -0,0 +1,38 @@ +#ifndef COPPER_H_ +#define COPPER_H_ + +#include "inttypes.h" + +#define COPPER_MOVE(reg, data) (((uint32_t)(reg) << 16) | ((uint32_t)(data) & 0xffff)) +#define COPPER_WAIT(x, y) \ + (0x0001fffe | ((uint32_t)((x) + 0x81) << 16) | ((uint32_t)((y) + 0x2c) << 24)) +#define COPPER_WAIT_OVERSCAN(x, y) \ + (0x0001fffe | ((uint32_t)(x) << 16) | ((uint32_t)(y) << 24)) +#define COPPER_VWAIT(s) (0x0001ff00 | ((uint32_t)((s) + 0x2c) << 24)) +#define COPPER_VWAIT_OVERSCAN(s) \ + (0x0001ff00 | ((uint32_t)(s) << 24)) +#define COPPER_END 0xfffffffe + +extern uint32_t *copperlist, *copperlist_end; + +enum { + COPPER_SINGLE = 1, + COPPER_DOUBLE = 2 +}; + +int init_copper(int maxlist, int nlists); +void cleanup_copper(void); + +/* enables copper DMA */ +void enable_copper(void); +/* disables copper DMA */ +void disable_copper(void); + +void clear_copper(void); +void add_copper(uint32_t cmd); +void sort_copper(void); /* TODO */ + +void swap_copper(void); + + +#endif /* COPPER_H_ */ diff -r 51422ea54b9d -r 48093e4bd99a src/hwregs.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/hwregs.h Wed Feb 21 18:00:45 2018 +0200 @@ -0,0 +1,428 @@ +#ifndef HWREGS_H_ +#define HWREGS_H_ + +#include "inttypes.h" + +#define REG_BASE_ADDR 0xdff000 + +#define REGN_BLTDDAT 0x000 +#define REGN_DMACONR 0x002 +#define REGN_VPOSR 0x004 +#define REGN_VHPOSR 0x006 +#define REGN_DSKDATR 0x008 +#define REGN_JOY0DAT 0x00a +#define REGN_JOY1DAT 0x00c +#define REGN_CLXDAT 0x00e +#define REGN_ADKCONR 0x010 +#define REGN_POT0DAT 0x012 +#define REGN_POT1DAT 0x014 +#define REGN_POTGOR 0x016 +#define REGN_SERDATR 0x018 +#define REGN_DSKBYTR 0x01a +#define REGN_INTENAR 0x01c +#define REGN_INTREQR 0x01e +#define REGN_DSKPTH 0x020 +#define REGN_DSKPTL 0x022 +#define REGN_DSKLEN 0x024 +#define REGN_DSKDAT 0x026 +#define REGN_REFPTR 0x028 +#define REGN_VPOSW 0x02a +#define REGN_VHPOSW 0x02c +#define REGN_COPCON 0x02e +#define REGN_SERDAT 0x030 +#define REGN_SERPER 0x032 +#define REGN_POTGO 0x034 +#define REGN_JOYTEST 0x036 +#define REGN_STREQU 0x038 +#define REGN_STRVBL 0x03a +#define REGN_STRHOR 0x03c +#define REGN_STRLONG 0x03e +#define REGN_BLTCON0 0x040 +#define REGN_BLTCON1 0x042 +#define REGN_BLTAFWM 0x044 +#define REGN_BLTALWM 0x046 +#define REGN_BLTCPTH 0x048 +#define REGN_BLTCPTL 0x04a +#define REGN_BLTBPTH 0x04c +#define REGN_BLTBPTL 0x04e +#define REGN_BLTAPTH 0x050 +#define REGN_BLTAPTL 0x052 +#define REGN_BLTDPTH 0x054 +#define REGN_BLTDPTL 0x056 +#define REGN_BLTSIZE 0x058 +#define REGN_BLTCON0L 0x05a +#define REGN_BLTSIZV 0x05c +#define REGN_BLTSIZH 0x05e +#define REGN_BLTCMOD 0x060 +#define REGN_BLTBMOD 0x062 +#define REGN_BLTAMOD 0x064 +#define REGN_BLTDMOD 0x066 +#define REGN_BLTCDAT 0x070 +#define REGN_BLTBDAT 0x072 +#define REGN_BLTADAT 0x074 +#define REGN_SPRHDAT 0x078 +#define REGN_DENISEID 0x07c +#define REGN_DSKSYNC 0x07e +#define REGN_COP1LCH 0x080 +#define REGN_COP1LCL 0x082 +#define REGN_COP2LCH 0x084 +#define REGN_COP2LCL 0x086 +#define REGN_CMPJMP1 0x088 +#define REGN_CMPJMP2 0x08a +#define REGN_COPINS 0x08c +#define REGN_DIWSTART 0x08e +#define REGN_DIWSTOP 0x090 +#define REGN_DDFSTART 0x092 +#define REGN_DDFSTOP 0x094 +#define REGN_DMACON 0x096 +#define REGN_CLXCON 0x098 +#define REGN_INTENA 0x09a +#define REGN_INTREQ 0x09c +#define REGN_ADKCON 0x09e + +#define REGN_AUDIO_LCH(c) (REGN_AUDIO0_BASE + (c) * 16 + 0) +#define REGN_AUDIO_LCL(c) (REGN_AUDIO0_BASE + (c) * 16 + 2) +#define REGN_AUDIO_LEN(c) (REGN_AUDIO0_BASE + (c) * 16 + 4) +#define REGN_AUDIO_PER(c) (REGN_AUDIO0_BASE + (c) * 16 + 6) +#define REGN_AUDIO_VOL(c) (REGN_AUDIO0_BASE + (c) * 16 + 8) +#define REGN_AUDIO_DAT(c) (REGN_AUDIO0_BASE + (c) * 16 + 10) + +#define REGN_AUDIO0_BASE 0x0a0 +#define REGN_AUD0LCH (REGN_AUDIO0_BASE + 0) +#define REGN_AUD0LCL (REGN_AUDIO0_BASE + 2) +#define REGN_AUD0LEN (REGN_AUDIO0_BASE + 4) +#define REGN_AUD0PER (REGN_AUDIO0_BASE + 6) +#define REGN_AUD0VOL (REGN_AUDIO0_BASE + 8) +#define REGN_AUD0DAT (REGN_AUDIO0_BASE + 10) +#define REGN_AUDIO1_BASE 0x0b0 +#define REGN_AUD1LCH (REGN_AUDIO1_BASE + 0) +#define REGN_AUD1LCL (REGN_AUDIO1_BASE + 2) +#define REGN_AUD1LEN (REGN_AUDIO1_BASE + 4) +#define REGN_AUD1PER (REGN_AUDIO1_BASE + 6) +#define REGN_AUD1VOL (REGN_AUDIO1_BASE + 8) +#define REGN_AUD1DAT (REGN_AUDIO1_BASE + 10) +#define REGN_AUDIO2_BASE 0x0c0 +#define REGN_AUD2LCH (REGN_AUDIO2_BASE + 0) +#define REGN_AUD2LCL (REGN_AUDIO2_BASE + 2) +#define REGN_AUD2LEN (REGN_AUDIO2_BASE + 4) +#define REGN_AUD2PER (REGN_AUDIO2_BASE + 6) +#define REGN_AUD2VOL (REGN_AUDIO2_BASE + 8) +#define REGN_AUD2DAT (REGN_AUDIO2_BASE + 10) +#define REGN_AUDIO3_BASE 0x0d0 +#define REGN_AUD3LCH (REGN_AUDIO3_BASE + 0) +#define REGN_AUD3LCL (REGN_AUDIO3_BASE + 2) +#define REGN_AUD3LEN (REGN_AUDIO3_BASE + 4) +#define REGN_AUD3PER (REGN_AUDIO3_BASE + 6) +#define REGN_AUD3VOL (REGN_AUDIO3_BASE + 8) +#define REGN_AUD3DAT (REGN_AUDIO3_BASE + 10) + +#define REGN_BPL1PTH 0x0e0 +#define REGN_BPL1PTL 0x0e2 +#define REGN_BPL2PTH 0x0e4 +#define REGN_BPL2PTL 0x0e6 +#define REGN_BPL3PTH 0x0e8 +#define REGN_BPL3PTL 0x0ea +#define REGN_BPL4PTH 0x0ec +#define REGN_BPL4PTL 0x0ee +#define REGN_BPL5PTH 0x0f0 +#define REGN_BPL5PTL 0x0f2 +#define REGN_BPL6PTH 0x0f4 +#define REGN_BPL6PTL 0x0f6 +#define REGN_BPLCON0 0x100 +#define REGN_BPLCON1 0x102 +#define REGN_BPLCON2 0x104 +#define REGN_BPLCON3 0x106 +#define REGN_BPL1MOD 0x108 +#define REGN_BPL2MOD 0x10a +#define REGN_BPL1DAT 0x110 +#define REGN_BPL2DAT 0x112 +#define REGN_BPL3DAT 0x114 +#define REGN_BPL4DAT 0x116 +#define REGN_BPL5DAT 0x118 +#define REGN_BPL6DAT 0x11a + +#define REGN_SPR0PTH 0x120 +#define REGN_SPR0PTL 0x122 +#define REGN_SPR1PTH 0x124 +#define REGN_SPR1PTL 0x126 +#define REGN_SPR2PTH 0x128 +#define REGN_SPR2PTL 0x12a +#define REGN_SPR3PTH 0x12c +#define REGN_SPR3PTL 0x12e +#define REGN_SPR4PTH 0x130 +#define REGN_SPR4PTL 0x132 +#define REGN_SPR5PTH 0x134 +#define REGN_SPR5PTL 0x136 +#define REGN_SPR6PTH 0x138 +#define REGN_SPR6PTL 0x13a +#define REGN_SPR7PTH 0x13c +#define REGN_SPR7PTL 0x13e + +#define REGN_SPRITE_POS(s) (REGN_SPRITE0_BASE + (s) * 8 + 0) +#define REGN_SPRITE_CTL(s) (REGN_SPRITE0_BASE + (s) * 8 + 2) +#define REGN_SPRITE_DATA(s) (REGN_SPRITE0_BASE + (s) * 8 + 4) +#define REGN_SPRITE_DATB(s) (REGN_SPRITE0_BASE + (s) * 8 + 6) + +#define REGN_SPRITE0_BASE 0x140 +#define REGN_SPR0POS REGN_SPRITE_POS(0) +#define REGN_SPR0CTL REGN_SPRITE_CTL(0) +#define REGN_SPR0DATA REGN_SPRITE_DATA(0) +#define REGN_SPR0DATB REGN_SPRITE_DATB(0) +#define REGN_SPRITE1_BASE 0x148 +#define REGN_SPR1POS REGN_SPRITE_POS(1) +#define REGN_SPR1CTL REGN_SPRITE_CTL(1) +#define REGN_SPR1DATA REGN_SPRITE_DATA(1) +#define REGN_SPR1DATB REGN_SPRITE_DATB(1) +#define REGN_SPRITE2_BASE 0x150 +#define REGN_SPR2POS REGN_SPRITE_POS(2) +#define REGN_SPR2CTL REGN_SPRITE_CTL(2) +#define REGN_SPR2DATA REGN_SPRITE_DATA(2) +#define REGN_SPR2DATB REGN_SPRITE_DATB(2) +#define REGN_SPRITE3_BASE 0x158 +#define REGN_SPR3POS REGN_SPRITE_POS(3) +#define REGN_SPR3CTL REGN_SPRITE_CTL(3) +#define REGN_SPR3DATA REGN_SPRITE_DATA(3) +#define REGN_SPR3DATB REGN_SPRITE_DATB(3) +#define REGN_SPRITE4_BASE 0x160 +#define REGN_SPR4POS REGN_SPRITE_POS(4) +#define REGN_SPR4CTL REGN_SPRITE_CTL(4) +#define REGN_SPR4DATA REGN_SPRITE_DATA(4) +#define REGN_SPR4DATB REGN_SPRITE_DATB(4) +#define REGN_SPRITE5_BASE 0x168 +#define REGN_SPR5POS REGN_SPRITE_POS(5) +#define REGN_SPR5CTL REGN_SPRITE_CTL(5) +#define REGN_SPR5DATA REGN_SPRITE_DATA(5) +#define REGN_SPR5DATB REGN_SPRITE_DATB(5) +#define REGN_SPRITE6_BASE 0x170 +#define REGN_SPR6POS REGN_SPRITE_POS(6) +#define REGN_SPR6CTL REGN_SPRITE_CTL(6) +#define REGN_SPR6DATA REGN_SPRITE_DATA(6) +#define REGN_SPR6DATB REGN_SPRITE_DATB(6) +#define REGN_SPRITE7_BASE 0x178 +#define REGN_SPR7POS REGN_SPRITE_POS(7) +#define REGN_SPR7CTL REGN_SPRITE_CTL(7) +#define REGN_SPR7DATA REGN_SPRITE_DATA(7) +#define REGN_SPR7DATB REGN_SPRITE_DATB(7) + +#define REGN_COLOR_BASE 0x180 +#define REGN_COLOR(idx) (REGN_COLOR_BASE + (idx) * 2) + +#define REGN_COLOR0 REGN_COLOR(0) +#define REGN_COLOR1 REGN_COLOR(1) +#define REGN_COLOR2 REGN_COLOR(2) +#define REGN_COLOR3 REGN_COLOR(3) +#define REGN_COLOR4 REGN_COLOR(4) +#define REGN_COLOR5 REGN_COLOR(5) +#define REGN_COLOR6 REGN_COLOR(6) +#define REGN_COLOR7 REGN_COLOR(7) +#define REGN_COLOR8 REGN_COLOR(8) +#define REGN_COLOR9 REGN_COLOR(9) +#define REGN_COLOR10 REGN_COLOR(10) +#define REGN_COLOR11 REGN_COLOR(11) +#define REGN_COLOR12 REGN_COLOR(12) +#define REGN_COLOR13 REGN_COLOR(13) +#define REGN_COLOR14 REGN_COLOR(14) +#define REGN_COLOR15 REGN_COLOR(15) +#define REGN_COLOR16 REGN_COLOR(16) +#define REGN_COLOR17 REGN_COLOR(17) +#define REGN_COLOR18 REGN_COLOR(18) +#define REGN_COLOR19 REGN_COLOR(19) +#define REGN_COLOR20 REGN_COLOR(20) +#define REGN_COLOR21 REGN_COLOR(21) +#define REGN_COLOR22 REGN_COLOR(22) +#define REGN_COLOR23 REGN_COLOR(23) +#define REGN_COLOR24 REGN_COLOR(24) +#define REGN_COLOR25 REGN_COLOR(25) +#define REGN_COLOR26 REGN_COLOR(26) +#define REGN_COLOR27 REGN_COLOR(27) +#define REGN_COLOR28 REGN_COLOR(28) +#define REGN_COLOR29 REGN_COLOR(29) +#define REGN_COLOR30 REGN_COLOR(30) +#define REGN_COLOR31 REGN_COLOR(31) + +#define REGN_HTOTAL 0x1c0 +#define REGN_HSSTOP 0x1c2 +#define REGN_HBSTART 0x1c4 +#define REGN_HBSTOP 0x1c6 +#define REGN_VTOTAL 0x1c8 +#define REGN_VSSTOP 0x1ca +#define REGN_VBSTART 0x1cc +#define REGN_VBSTOP 0x1ce +#define REGN_BEAMCON0 0x1dc +#define REGN_HSSTART 0x1de +#define REGN_VSSTART 0x1e0 +#define REGN_HCENTER 0x1e2 +#define REGN_DIWHIGH 0x1e4 + +#define REGN_COP1LCH 0x080 +#define REGN_COP1LCL 0x082 +#define REGN_COP2LCH 0x084 +#define REGN_COP2LCL 0x086 +#define REGN_COPJMP1 0x088 +#define REGN_COPJMP2 0x08a + +#define REG(r) (*(volatile uint16_t*)(REG_BASE_ADDR | (r))) + +#define REG_CIAA_PORTA *(volatile uint8_t*)0xbfe001 + +#define REG_INTENA REG(REGN_INTENA) +#define REG_INTENAR REG(REGN_INTENAR) +#define REG_INTREQ REG(REGN_INTREQ) +#define REG_INTREQR REG(REGN_INTREQR) +#define REG_ADKCON REG(REGN_ADKCON) +#define REG_ADKCONR REG(REGN_ADKCONR) +#define REG_DMACON REG(REGN_DMACON) +#define REG_DMACONR REG(REGN_DMACONR) +#define REG_BPLCON0 REG(REGN_BPLCON0) +#define REG_BPLCON1 REG(REGN_BPLCON1) +#define REG_BPLCON2 REG(REGN_BPLCON2) +#define REG_BPL1PTH REG(REGN_BPL1PTH) +#define REG_BPL2PTH REG(REGN_BPL2PTH) +#define REG_BPL3PTH REG(REGN_BPL3PTH) +#define REG_BPL4PTH REG(REGN_BPL4PTH) +#define REG_BPL5PTH REG(REGN_BPL5PTH) +#define REG_BPL6PTH REG(REGN_BPL6PTH) +#define REG_BPL1PTL REG(REGN_BPL1PTL) +#define REG_BPL2PTL REG(REGN_BPL2PTL) +#define REG_BPL3PTL REG(REGN_BPL3PTL) +#define REG_BPL4PTL REG(REGN_BPL4PTL) +#define REG_BPL5PTL REG(REGN_BPL5PTL) +#define REG_BPL6PTL REG(REGN_BPL6PTL) +#define REG32_BPL1PT *(volatile uint32_t*)(REG_BASE_ADDR | REGN_BPL1PTH) +#define REG32_BPL2PT *(volatile uint32_t*)(REG_BASE_ADDR | REGN_BPL2PTH) +#define REG32_BPL3PT *(volatile uint32_t*)(REG_BASE_ADDR | REGN_BPL3PTH) +#define REG32_BPL4PT *(volatile uint32_t*)(REG_BASE_ADDR | REGN_BPL4PTH) +#define REG32_BPL5PT *(volatile uint32_t*)(REG_BASE_ADDR | REGN_BPL5PTH) +#define REG32_BPL6PT *(volatile uint32_t*)(REG_BASE_ADDR | REGN_BPL6PTH) +#define REG_BPL1MOD REG(REGN_BPL1MOD) +#define REG_BPL2MOD REG(REGN_BPL2MOD) +#define REG_DIWSTART REG(REGN_DIWSTART) +#define REG_DIWSTOP REG(REGN_DIWSTOP) +#define REG_DDFSTART REG(REGN_DDFSTART) +#define REG_DDFSTOP REG(REGN_DDFSTOP) +#define REG_VPOS REG(REGN_VPOS) +#define REG_VPOSR REG(REGN_VPOSR) +#define REG_VHPOS REG(REGN_VHPOS) +#define REG_VHPOSR REG(REGN_VHPOSR) +#define REG32_VPOSR *(volatile uint32_t*)(REG_BASE_ADDR | REGN_VPOSR) + +#define REG_COLOR_PTR ((volatile uint16_t*)(REG_BASE_ADDR | REGN_COLOR0)) +#define REG_COLOR0 REG(REGN_COLOR0) +#define REG_COLOR1 REG(REGN_COLOR1) +#define REG_COLOR2 REG(REGN_COLOR2) +#define REG_COLOR3 REG(REGN_COLOR3) +#define REG_COLOR4 REG(REGN_COLOR4) +#define REG_COLOR5 REG(REGN_COLOR5) +#define REG_COLOR6 REG(REGN_COLOR6) +#define REG_COLOR7 REG(REGN_COLOR7) +#define REG_COLOR8 REG(REGN_COLOR8) +#define REG_COLOR9 REG(REGN_COLOR9) +#define REG_COLOR10 REG(REGN_COLOR10) +#define REG_COLOR11 REG(REGN_COLOR11) +#define REG_COLOR12 REG(REGN_COLOR12) +#define REG_COLOR13 REG(REGN_COLOR13) +#define REG_COLOR14 REG(REGN_COLOR14) +#define REG_COLOR15 REG(REGN_COLOR15) +#define REG_COLOR16 REG(REGN_COLOR16) +#define REG_COLOR17 REG(REGN_COLOR17) +#define REG_COLOR18 REG(REGN_COLOR18) +#define REG_COLOR19 REG(REGN_COLOR19) +#define REG_COLOR20 REG(REGN_COLOR20) +#define REG_COLOR21 REG(REGN_COLOR21) +#define REG_COLOR22 REG(REGN_COLOR22) +#define REG_COLOR23 REG(REGN_COLOR23) +#define REG_COLOR24 REG(REGN_COLOR24) +#define REG_COLOR25 REG(REGN_COLOR25) +#define REG_COLOR26 REG(REGN_COLOR26) +#define REG_COLOR27 REG(REGN_COLOR27) +#define REG_COLOR28 REG(REGN_COLOR28) +#define REG_COLOR29 REG(REGN_COLOR29) +#define REG_COLOR30 REG(REGN_COLOR30) +#define REG_COLOR31 REG(REGN_COLOR31) + +#define REG32_COP1LC *(volatile uint32_t*)(REG_BASE_ADDR | REGN_COP1LCH) +#define REG32_COP2LC *(volatile uint32_t*)(REG_BASE_ADDR | REGN_COP2LCH) +#define REG_COPJMP1 REG(REGN_COPJMP1) +#define REG_COPJMP2 REG(REGN_COPJMP2) + +/* ------ bits ------- */ +#define SETBITS(x) ((x) | 0x8000) +#define CLRBITS(x) (x) + +/* interrupt numbers */ +enum { + INTR_TBE, + INTR_DSKBLK, + INTR_SOFT, + INTR_PORTS, + INTR_COPPER, + INTR_VERTB, + INTR_BLITTER, + INTR_AUDIO0, + INTR_AUDIO1, + INTR_AUDIO2, + INTR_AUDIO3, + INTR_RBF, + INTR_DSKSYN, + INTR_EXTER +}; + +/* interrupt enable flags */ +enum { + INTEN_TBE = 0x0001, + INTEN_DSKBLK = 0x0002, + INTEN_SOFT = 0x0004, + INTEN_PORTS = 0x0008, + INTEN_COPPER = 0x0010, + INTEN_VERTB = 0x0020, + INTEN_BLITTER = 0x0040, + INTEN_AUDIO0 = 0x0080, + INTEN_AUDIO1 = 0x0100, + INTEN_AUDIO2 = 0x0200, + INTEN_AUDIO3 = 0x0400, + INTEN_RBF = 0x0800, + INTEN_DSKSYN = 0x1000, + INTEN_EXTER = 0x2000, + INTEN_MASTER = 0x4000, + + INTEN_ALL = 0x7fff +}; + +/* DMA control flags */ +enum { + DMA_AUD0 = 0x0001, + DMA_AUD1 = 0x0002, + DMA_AUD2 = 0x0004, + DMA_AUD3 = 0x0008, + DMA_AUDIO = 0x000f, /* all the above */ + DMA_DISK = 0x0010, + DMA_SPRITE = 0x0020, + DMA_BLITTER = 0x0040, + DMA_COPPER = 0x0080, + DMA_BPL = 0x0100, + DMA_MASTER = 0x0200, + + DMA_ALL = 0x01ff +}; + +/* Bitplane control */ +enum { + BPLCON0_ERSY = 0x0002, + BPLCON0_LACE = 0x0004, + BPLCON0_LPEN = 0x0008, + BPLCON0_GAUD = 0x0100, + BPLCON0_COLOR = 0x0200, + BPLCON0_DBLPF = 0x0400, + BPLCON0_HOMOD = 0x0800, + BPLCON0_BPU0 = 0x1000, + BPLCON0_BPU1 = 0x2000, + BPLCON0_BPU2 = 0x4000, + BPLCON0_HIRES = 0x8000 +}; + +#define BPLCON0_COUNT(x) ((x) << 12) + +#define CIAA_PA_FIR0 0x40 +#define CIAA_PA_FIR1 0x80 + +#endif /* HWREGS_H_ */ diff -r 51422ea54b9d -r 48093e4bd99a src/intr.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/intr.h Wed Feb 21 18:00:45 2018 +0200 @@ -0,0 +1,7 @@ +#ifndef INTR_H_ +#define INTR_H_ + +#define enable_intr() asm volatile ("andi.w #0xf8ff, %sr") +#define disable_intr() asm volatile ("ori.w #0x0300, %sr") + +#endif /* INTR_H_ */ diff -r 51422ea54b9d -r 48093e4bd99a src/intr.s --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/intr.s Wed Feb 21 18:00:45 2018 +0200 @@ -0,0 +1,13 @@ + .text + + .global intr_debug +intr_debug: + movem.l %d0-%a6, -(%sp) + move.w dbgval, %d0 + move.w %d0, 0xdff180 + not.w %d0 + move.w %d0, dbgval + movem.l (%sp)+, %d0-%a6 + rte + +dbgval: .word 0x00f diff -r 51422ea54b9d -r 48093e4bd99a src/inttypes.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/inttypes.h Wed Feb 21 18:00:45 2018 +0200 @@ -0,0 +1,11 @@ +#ifndef INTTYPES_H_ +#define INTTYPES_H_ + +typedef signed char int8_t; +typedef unsigned char uint8_t; +typedef short int16_t; +typedef unsigned short uint16_t; +typedef long int32_t; +typedef unsigned long uint32_t; + +#endif /* INTTYPES_H_ */ diff -r 51422ea54b9d -r 48093e4bd99a src/main.c --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/main.c Wed Feb 21 18:00:45 2018 +0200 @@ -0,0 +1,59 @@ +#include "hwregs.h" +#include "intr.h" +#include "copper.h" + +void wait_vpos(int x); +void wait_vblank(void); + +#define BPLSZ (320 / 8 * 256) +static unsigned char fb0[BPLSZ]; + +int main(void) +{ + uint32_t fb0_addr = (uint32_t)fb0; + + REG_INTENA = SETBITS(INTEN_VERTB | INTEN_MASTER); + + REG_DMACON = CLRBITS(DMA_ALL); + REG_BPLCON0 = BPLCON0_COUNT(0) | BPLCON0_COLOR; + REG_BPLCON1 = 0; + REG_DIWSTART = 0x2981; + REG_DIWSTOP = 0x29c1; + REG_DDFSTART = 0x38; + REG_DDFSTOP = 0xd0; + + REG_COLOR0 = 0x00f; + REG_COLOR1 = 0xff0; + + init_copper(0, 0); + + wait_vblank(); + add_copper(COPPER_MOVE(REGN_BPL1PTH, fb0_addr >> 16)); + add_copper(COPPER_MOVE(REGN_BPL1PTL, fb0_addr)); + + add_copper(COPPER_VWAIT(64)); + add_copper(COPPER_MOVE(REGN_COLOR0, 0xf00)); + add_copper(COPPER_VWAIT(70)); + add_copper(COPPER_MOVE(REGN_COLOR0, 0x00f)); + + add_copper(COPPER_END); + + fb0[128 * 320 / 8] = 8; + + REG_DMACON = SETBITS(DMA_COPPER | DMA_MASTER); + enable_intr(); + + for(;;); + return 0; +} + +void wait_vpos(int x) +{ + x <<= 8; + while((REG32_VPOSR & 0x1ff00) < x); +} + +void wait_vblank(void) +{ + wait_vpos(300); +} diff -r 51422ea54b9d -r 48093e4bd99a src/startup.s --- a/src/startup.s Wed Feb 21 12:00:13 2018 +0200 +++ b/src/startup.s Wed Feb 21 18:00:45 2018 +0200 @@ -1,12 +1,16 @@ | vi:filetype=gas68k: - .text - - .equ REG_COL0, 0xdff180 - .global start .global halt_cpu + .extern main -start: + .section .text.startup + + | enter supervisor mode (assumes VBR=0) + move.l #super, 0x80 + trap #0 +super: + ori.w #0x0300, %sr | disable interrupts + | zero the .bss section move.l #_bss_start, %a0 move.l #_bss_end, %a1 @@ -18,10 +22,10 @@ 1: | setup the stack move.l #_stacktop, %sp + andi.w #0xf8ff, %sr | enable interrupts - | test output - move.w #0xf0f, REG_COL0 -0: bra.b 0b | infloop + jsr main +0: bra.b 0b halt_cpu: stop #0x2700