1.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.2 +++ b/src/hwregs.h	Wed Feb 21 18:00:45 2018 +0200
     1.3 @@ -0,0 +1,428 @@
     1.4 +#ifndef HWREGS_H_
     1.5 +#define HWREGS_H_
     1.6 +
     1.7 +#include "inttypes.h"
     1.8 +
     1.9 +#define REG_BASE_ADDR	0xdff000
    1.10 +
    1.11 +#define REGN_BLTDDAT	0x000
    1.12 +#define REGN_DMACONR	0x002
    1.13 +#define REGN_VPOSR		0x004
    1.14 +#define REGN_VHPOSR		0x006
    1.15 +#define REGN_DSKDATR	0x008
    1.16 +#define REGN_JOY0DAT	0x00a
    1.17 +#define REGN_JOY1DAT	0x00c
    1.18 +#define REGN_CLXDAT		0x00e
    1.19 +#define REGN_ADKCONR	0x010
    1.20 +#define REGN_POT0DAT	0x012
    1.21 +#define REGN_POT1DAT	0x014
    1.22 +#define REGN_POTGOR		0x016
    1.23 +#define REGN_SERDATR	0x018
    1.24 +#define REGN_DSKBYTR	0x01a
    1.25 +#define REGN_INTENAR	0x01c
    1.26 +#define REGN_INTREQR	0x01e
    1.27 +#define REGN_DSKPTH		0x020
    1.28 +#define REGN_DSKPTL		0x022
    1.29 +#define REGN_DSKLEN		0x024
    1.30 +#define REGN_DSKDAT		0x026
    1.31 +#define REGN_REFPTR		0x028
    1.32 +#define REGN_VPOSW		0x02a
    1.33 +#define REGN_VHPOSW		0x02c
    1.34 +#define REGN_COPCON		0x02e
    1.35 +#define REGN_SERDAT		0x030
    1.36 +#define REGN_SERPER		0x032
    1.37 +#define REGN_POTGO		0x034
    1.38 +#define REGN_JOYTEST	0x036
    1.39 +#define REGN_STREQU		0x038
    1.40 +#define REGN_STRVBL		0x03a
    1.41 +#define REGN_STRHOR		0x03c
    1.42 +#define REGN_STRLONG	0x03e
    1.43 +#define REGN_BLTCON0	0x040
    1.44 +#define REGN_BLTCON1	0x042
    1.45 +#define REGN_BLTAFWM	0x044
    1.46 +#define REGN_BLTALWM	0x046
    1.47 +#define REGN_BLTCPTH	0x048
    1.48 +#define REGN_BLTCPTL	0x04a
    1.49 +#define REGN_BLTBPTH	0x04c
    1.50 +#define REGN_BLTBPTL	0x04e
    1.51 +#define REGN_BLTAPTH	0x050
    1.52 +#define REGN_BLTAPTL	0x052
    1.53 +#define REGN_BLTDPTH	0x054
    1.54 +#define REGN_BLTDPTL	0x056
    1.55 +#define REGN_BLTSIZE	0x058
    1.56 +#define REGN_BLTCON0L	0x05a
    1.57 +#define REGN_BLTSIZV	0x05c
    1.58 +#define REGN_BLTSIZH	0x05e
    1.59 +#define REGN_BLTCMOD	0x060
    1.60 +#define REGN_BLTBMOD	0x062
    1.61 +#define REGN_BLTAMOD	0x064
    1.62 +#define REGN_BLTDMOD	0x066
    1.63 +#define REGN_BLTCDAT	0x070
    1.64 +#define REGN_BLTBDAT	0x072
    1.65 +#define REGN_BLTADAT	0x074
    1.66 +#define REGN_SPRHDAT	0x078
    1.67 +#define REGN_DENISEID	0x07c
    1.68 +#define REGN_DSKSYNC	0x07e
    1.69 +#define REGN_COP1LCH	0x080
    1.70 +#define REGN_COP1LCL	0x082
    1.71 +#define REGN_COP2LCH	0x084
    1.72 +#define REGN_COP2LCL	0x086
    1.73 +#define REGN_CMPJMP1	0x088
    1.74 +#define REGN_CMPJMP2	0x08a
    1.75 +#define REGN_COPINS		0x08c
    1.76 +#define REGN_DIWSTART	0x08e
    1.77 +#define REGN_DIWSTOP	0x090
    1.78 +#define REGN_DDFSTART	0x092
    1.79 +#define REGN_DDFSTOP	0x094
    1.80 +#define REGN_DMACON		0x096
    1.81 +#define REGN_CLXCON		0x098
    1.82 +#define REGN_INTENA		0x09a
    1.83 +#define REGN_INTREQ		0x09c
    1.84 +#define REGN_ADKCON		0x09e
    1.85 +
    1.86 +#define REGN_AUDIO_LCH(c)	(REGN_AUDIO0_BASE + (c) * 16 + 0)
    1.87 +#define REGN_AUDIO_LCL(c)	(REGN_AUDIO0_BASE + (c) * 16 + 2)
    1.88 +#define REGN_AUDIO_LEN(c)	(REGN_AUDIO0_BASE + (c) * 16 + 4)
    1.89 +#define REGN_AUDIO_PER(c)	(REGN_AUDIO0_BASE + (c) * 16 + 6)
    1.90 +#define REGN_AUDIO_VOL(c)	(REGN_AUDIO0_BASE + (c) * 16 + 8)
    1.91 +#define REGN_AUDIO_DAT(c)	(REGN_AUDIO0_BASE + (c) * 16 + 10)
    1.92 +
    1.93 +#define REGN_AUDIO0_BASE	0x0a0
    1.94 +#define REGN_AUD0LCH		(REGN_AUDIO0_BASE + 0)
    1.95 +#define REGN_AUD0LCL		(REGN_AUDIO0_BASE + 2)
    1.96 +#define REGN_AUD0LEN		(REGN_AUDIO0_BASE + 4)
    1.97 +#define REGN_AUD0PER		(REGN_AUDIO0_BASE + 6)
    1.98 +#define REGN_AUD0VOL		(REGN_AUDIO0_BASE + 8)
    1.99 +#define REGN_AUD0DAT		(REGN_AUDIO0_BASE + 10)
   1.100 +#define REGN_AUDIO1_BASE	0x0b0
   1.101 +#define REGN_AUD1LCH		(REGN_AUDIO1_BASE + 0)
   1.102 +#define REGN_AUD1LCL		(REGN_AUDIO1_BASE + 2)
   1.103 +#define REGN_AUD1LEN		(REGN_AUDIO1_BASE + 4)
   1.104 +#define REGN_AUD1PER		(REGN_AUDIO1_BASE + 6)
   1.105 +#define REGN_AUD1VOL		(REGN_AUDIO1_BASE + 8)
   1.106 +#define REGN_AUD1DAT		(REGN_AUDIO1_BASE + 10)
   1.107 +#define REGN_AUDIO2_BASE	0x0c0
   1.108 +#define REGN_AUD2LCH		(REGN_AUDIO2_BASE + 0)
   1.109 +#define REGN_AUD2LCL		(REGN_AUDIO2_BASE + 2)
   1.110 +#define REGN_AUD2LEN		(REGN_AUDIO2_BASE + 4)
   1.111 +#define REGN_AUD2PER		(REGN_AUDIO2_BASE + 6)
   1.112 +#define REGN_AUD2VOL		(REGN_AUDIO2_BASE + 8)
   1.113 +#define REGN_AUD2DAT		(REGN_AUDIO2_BASE + 10)
   1.114 +#define REGN_AUDIO3_BASE	0x0d0
   1.115 +#define REGN_AUD3LCH		(REGN_AUDIO3_BASE + 0)
   1.116 +#define REGN_AUD3LCL		(REGN_AUDIO3_BASE + 2)
   1.117 +#define REGN_AUD3LEN		(REGN_AUDIO3_BASE + 4)
   1.118 +#define REGN_AUD3PER		(REGN_AUDIO3_BASE + 6)
   1.119 +#define REGN_AUD3VOL		(REGN_AUDIO3_BASE + 8)
   1.120 +#define REGN_AUD3DAT		(REGN_AUDIO3_BASE + 10)
   1.121 +
   1.122 +#define REGN_BPL1PTH	0x0e0
   1.123 +#define REGN_BPL1PTL	0x0e2
   1.124 +#define REGN_BPL2PTH	0x0e4
   1.125 +#define REGN_BPL2PTL	0x0e6
   1.126 +#define REGN_BPL3PTH	0x0e8
   1.127 +#define REGN_BPL3PTL	0x0ea
   1.128 +#define REGN_BPL4PTH	0x0ec
   1.129 +#define REGN_BPL4PTL	0x0ee
   1.130 +#define REGN_BPL5PTH	0x0f0
   1.131 +#define REGN_BPL5PTL	0x0f2
   1.132 +#define REGN_BPL6PTH	0x0f4
   1.133 +#define REGN_BPL6PTL	0x0f6
   1.134 +#define REGN_BPLCON0	0x100
   1.135 +#define REGN_BPLCON1	0x102
   1.136 +#define REGN_BPLCON2	0x104
   1.137 +#define REGN_BPLCON3	0x106
   1.138 +#define REGN_BPL1MOD	0x108
   1.139 +#define REGN_BPL2MOD	0x10a
   1.140 +#define REGN_BPL1DAT	0x110
   1.141 +#define REGN_BPL2DAT	0x112
   1.142 +#define REGN_BPL3DAT	0x114
   1.143 +#define REGN_BPL4DAT	0x116
   1.144 +#define REGN_BPL5DAT	0x118
   1.145 +#define REGN_BPL6DAT	0x11a
   1.146 +
   1.147 +#define REGN_SPR0PTH	0x120
   1.148 +#define REGN_SPR0PTL	0x122
   1.149 +#define REGN_SPR1PTH	0x124
   1.150 +#define REGN_SPR1PTL	0x126
   1.151 +#define REGN_SPR2PTH	0x128
   1.152 +#define REGN_SPR2PTL	0x12a
   1.153 +#define REGN_SPR3PTH	0x12c
   1.154 +#define REGN_SPR3PTL	0x12e
   1.155 +#define REGN_SPR4PTH	0x130
   1.156 +#define REGN_SPR4PTL	0x132
   1.157 +#define REGN_SPR5PTH	0x134
   1.158 +#define REGN_SPR5PTL	0x136
   1.159 +#define REGN_SPR6PTH	0x138
   1.160 +#define REGN_SPR6PTL	0x13a
   1.161 +#define REGN_SPR7PTH	0x13c
   1.162 +#define REGN_SPR7PTL	0x13e
   1.163 +
   1.164 +#define REGN_SPRITE_POS(s)	(REGN_SPRITE0_BASE + (s) * 8 + 0)
   1.165 +#define REGN_SPRITE_CTL(s)	(REGN_SPRITE0_BASE + (s) * 8 + 2)
   1.166 +#define REGN_SPRITE_DATA(s)	(REGN_SPRITE0_BASE + (s) * 8 + 4)
   1.167 +#define REGN_SPRITE_DATB(s)	(REGN_SPRITE0_BASE + (s) * 8 + 6)
   1.168 +
   1.169 +#define REGN_SPRITE0_BASE	0x140
   1.170 +#define REGN_SPR0POS		REGN_SPRITE_POS(0)
   1.171 +#define REGN_SPR0CTL		REGN_SPRITE_CTL(0)
   1.172 +#define REGN_SPR0DATA		REGN_SPRITE_DATA(0)
   1.173 +#define REGN_SPR0DATB		REGN_SPRITE_DATB(0)
   1.174 +#define REGN_SPRITE1_BASE	0x148
   1.175 +#define REGN_SPR1POS		REGN_SPRITE_POS(1)
   1.176 +#define REGN_SPR1CTL		REGN_SPRITE_CTL(1)
   1.177 +#define REGN_SPR1DATA		REGN_SPRITE_DATA(1)
   1.178 +#define REGN_SPR1DATB		REGN_SPRITE_DATB(1)
   1.179 +#define REGN_SPRITE2_BASE	0x150
   1.180 +#define REGN_SPR2POS		REGN_SPRITE_POS(2)
   1.181 +#define REGN_SPR2CTL		REGN_SPRITE_CTL(2)
   1.182 +#define REGN_SPR2DATA		REGN_SPRITE_DATA(2)
   1.183 +#define REGN_SPR2DATB		REGN_SPRITE_DATB(2)
   1.184 +#define REGN_SPRITE3_BASE	0x158
   1.185 +#define REGN_SPR3POS		REGN_SPRITE_POS(3)
   1.186 +#define REGN_SPR3CTL		REGN_SPRITE_CTL(3)
   1.187 +#define REGN_SPR3DATA		REGN_SPRITE_DATA(3)
   1.188 +#define REGN_SPR3DATB		REGN_SPRITE_DATB(3)
   1.189 +#define REGN_SPRITE4_BASE	0x160
   1.190 +#define REGN_SPR4POS		REGN_SPRITE_POS(4)
   1.191 +#define REGN_SPR4CTL		REGN_SPRITE_CTL(4)
   1.192 +#define REGN_SPR4DATA		REGN_SPRITE_DATA(4)
   1.193 +#define REGN_SPR4DATB		REGN_SPRITE_DATB(4)
   1.194 +#define REGN_SPRITE5_BASE	0x168
   1.195 +#define REGN_SPR5POS		REGN_SPRITE_POS(5)
   1.196 +#define REGN_SPR5CTL		REGN_SPRITE_CTL(5)
   1.197 +#define REGN_SPR5DATA		REGN_SPRITE_DATA(5)
   1.198 +#define REGN_SPR5DATB		REGN_SPRITE_DATB(5)
   1.199 +#define REGN_SPRITE6_BASE	0x170
   1.200 +#define REGN_SPR6POS		REGN_SPRITE_POS(6)
   1.201 +#define REGN_SPR6CTL		REGN_SPRITE_CTL(6)
   1.202 +#define REGN_SPR6DATA		REGN_SPRITE_DATA(6)
   1.203 +#define REGN_SPR6DATB		REGN_SPRITE_DATB(6)
   1.204 +#define REGN_SPRITE7_BASE	0x178
   1.205 +#define REGN_SPR7POS		REGN_SPRITE_POS(7)
   1.206 +#define REGN_SPR7CTL		REGN_SPRITE_CTL(7)
   1.207 +#define REGN_SPR7DATA		REGN_SPRITE_DATA(7)
   1.208 +#define REGN_SPR7DATB		REGN_SPRITE_DATB(7)
   1.209 +
   1.210 +#define REGN_COLOR_BASE		0x180
   1.211 +#define REGN_COLOR(idx)		(REGN_COLOR_BASE + (idx) * 2)
   1.212 +
   1.213 +#define REGN_COLOR0			REGN_COLOR(0)
   1.214 +#define REGN_COLOR1			REGN_COLOR(1)
   1.215 +#define REGN_COLOR2			REGN_COLOR(2)
   1.216 +#define REGN_COLOR3			REGN_COLOR(3)
   1.217 +#define REGN_COLOR4			REGN_COLOR(4)
   1.218 +#define REGN_COLOR5			REGN_COLOR(5)
   1.219 +#define REGN_COLOR6			REGN_COLOR(6)
   1.220 +#define REGN_COLOR7			REGN_COLOR(7)
   1.221 +#define REGN_COLOR8			REGN_COLOR(8)
   1.222 +#define REGN_COLOR9			REGN_COLOR(9)
   1.223 +#define REGN_COLOR10		REGN_COLOR(10)
   1.224 +#define REGN_COLOR11		REGN_COLOR(11)
   1.225 +#define REGN_COLOR12		REGN_COLOR(12)
   1.226 +#define REGN_COLOR13		REGN_COLOR(13)
   1.227 +#define REGN_COLOR14		REGN_COLOR(14)
   1.228 +#define REGN_COLOR15		REGN_COLOR(15)
   1.229 +#define REGN_COLOR16		REGN_COLOR(16)
   1.230 +#define REGN_COLOR17		REGN_COLOR(17)
   1.231 +#define REGN_COLOR18		REGN_COLOR(18)
   1.232 +#define REGN_COLOR19		REGN_COLOR(19)
   1.233 +#define REGN_COLOR20		REGN_COLOR(20)
   1.234 +#define REGN_COLOR21		REGN_COLOR(21)
   1.235 +#define REGN_COLOR22		REGN_COLOR(22)
   1.236 +#define REGN_COLOR23		REGN_COLOR(23)
   1.237 +#define REGN_COLOR24		REGN_COLOR(24)
   1.238 +#define REGN_COLOR25		REGN_COLOR(25)
   1.239 +#define REGN_COLOR26		REGN_COLOR(26)
   1.240 +#define REGN_COLOR27		REGN_COLOR(27)
   1.241 +#define REGN_COLOR28		REGN_COLOR(28)
   1.242 +#define REGN_COLOR29		REGN_COLOR(29)
   1.243 +#define REGN_COLOR30		REGN_COLOR(30)
   1.244 +#define REGN_COLOR31		REGN_COLOR(31)
   1.245 +
   1.246 +#define REGN_HTOTAL		0x1c0
   1.247 +#define REGN_HSSTOP		0x1c2
   1.248 +#define REGN_HBSTART	0x1c4
   1.249 +#define REGN_HBSTOP		0x1c6
   1.250 +#define REGN_VTOTAL		0x1c8
   1.251 +#define REGN_VSSTOP		0x1ca
   1.252 +#define REGN_VBSTART	0x1cc
   1.253 +#define REGN_VBSTOP		0x1ce
   1.254 +#define REGN_BEAMCON0	0x1dc
   1.255 +#define REGN_HSSTART	0x1de
   1.256 +#define REGN_VSSTART	0x1e0
   1.257 +#define REGN_HCENTER	0x1e2
   1.258 +#define REGN_DIWHIGH	0x1e4
   1.259 +
   1.260 +#define REGN_COP1LCH	0x080
   1.261 +#define REGN_COP1LCL	0x082
   1.262 +#define REGN_COP2LCH	0x084
   1.263 +#define REGN_COP2LCL	0x086
   1.264 +#define REGN_COPJMP1	0x088
   1.265 +#define REGN_COPJMP2	0x08a
   1.266 +
   1.267 +#define REG(r)	(*(volatile uint16_t*)(REG_BASE_ADDR | (r)))
   1.268 +
   1.269 +#define REG_CIAA_PORTA	*(volatile uint8_t*)0xbfe001
   1.270 +
   1.271 +#define REG_INTENA		REG(REGN_INTENA)
   1.272 +#define REG_INTENAR		REG(REGN_INTENAR)
   1.273 +#define REG_INTREQ		REG(REGN_INTREQ)
   1.274 +#define REG_INTREQR		REG(REGN_INTREQR)
   1.275 +#define REG_ADKCON		REG(REGN_ADKCON)
   1.276 +#define REG_ADKCONR		REG(REGN_ADKCONR)
   1.277 +#define REG_DMACON		REG(REGN_DMACON)
   1.278 +#define REG_DMACONR		REG(REGN_DMACONR)
   1.279 +#define REG_BPLCON0		REG(REGN_BPLCON0)
   1.280 +#define REG_BPLCON1		REG(REGN_BPLCON1)
   1.281 +#define REG_BPLCON2		REG(REGN_BPLCON2)
   1.282 +#define REG_BPL1PTH		REG(REGN_BPL1PTH)
   1.283 +#define REG_BPL2PTH		REG(REGN_BPL2PTH)
   1.284 +#define REG_BPL3PTH		REG(REGN_BPL3PTH)
   1.285 +#define REG_BPL4PTH		REG(REGN_BPL4PTH)
   1.286 +#define REG_BPL5PTH		REG(REGN_BPL5PTH)
   1.287 +#define REG_BPL6PTH		REG(REGN_BPL6PTH)
   1.288 +#define REG_BPL1PTL		REG(REGN_BPL1PTL)
   1.289 +#define REG_BPL2PTL		REG(REGN_BPL2PTL)
   1.290 +#define REG_BPL3PTL		REG(REGN_BPL3PTL)
   1.291 +#define REG_BPL4PTL		REG(REGN_BPL4PTL)
   1.292 +#define REG_BPL5PTL		REG(REGN_BPL5PTL)
   1.293 +#define REG_BPL6PTL		REG(REGN_BPL6PTL)
   1.294 +#define REG32_BPL1PT	*(volatile uint32_t*)(REG_BASE_ADDR | REGN_BPL1PTH)
   1.295 +#define REG32_BPL2PT	*(volatile uint32_t*)(REG_BASE_ADDR | REGN_BPL2PTH)
   1.296 +#define REG32_BPL3PT	*(volatile uint32_t*)(REG_BASE_ADDR | REGN_BPL3PTH)
   1.297 +#define REG32_BPL4PT	*(volatile uint32_t*)(REG_BASE_ADDR | REGN_BPL4PTH)
   1.298 +#define REG32_BPL5PT	*(volatile uint32_t*)(REG_BASE_ADDR | REGN_BPL5PTH)
   1.299 +#define REG32_BPL6PT	*(volatile uint32_t*)(REG_BASE_ADDR | REGN_BPL6PTH)
   1.300 +#define REG_BPL1MOD		REG(REGN_BPL1MOD)
   1.301 +#define REG_BPL2MOD		REG(REGN_BPL2MOD)
   1.302 +#define REG_DIWSTART	REG(REGN_DIWSTART)
   1.303 +#define REG_DIWSTOP		REG(REGN_DIWSTOP)
   1.304 +#define REG_DDFSTART	REG(REGN_DDFSTART)
   1.305 +#define REG_DDFSTOP		REG(REGN_DDFSTOP)
   1.306 +#define REG_VPOS		REG(REGN_VPOS)
   1.307 +#define REG_VPOSR		REG(REGN_VPOSR)
   1.308 +#define REG_VHPOS		REG(REGN_VHPOS)
   1.309 +#define REG_VHPOSR		REG(REGN_VHPOSR)
   1.310 +#define REG32_VPOSR		*(volatile uint32_t*)(REG_BASE_ADDR | REGN_VPOSR)
   1.311 +
   1.312 +#define REG_COLOR_PTR	((volatile uint16_t*)(REG_BASE_ADDR | REGN_COLOR0))
   1.313 +#define REG_COLOR0		REG(REGN_COLOR0)
   1.314 +#define REG_COLOR1		REG(REGN_COLOR1)
   1.315 +#define REG_COLOR2		REG(REGN_COLOR2)
   1.316 +#define REG_COLOR3		REG(REGN_COLOR3)
   1.317 +#define REG_COLOR4		REG(REGN_COLOR4)
   1.318 +#define REG_COLOR5		REG(REGN_COLOR5)
   1.319 +#define REG_COLOR6		REG(REGN_COLOR6)
   1.320 +#define REG_COLOR7		REG(REGN_COLOR7)
   1.321 +#define REG_COLOR8		REG(REGN_COLOR8)
   1.322 +#define REG_COLOR9		REG(REGN_COLOR9)
   1.323 +#define REG_COLOR10		REG(REGN_COLOR10)
   1.324 +#define REG_COLOR11		REG(REGN_COLOR11)
   1.325 +#define REG_COLOR12		REG(REGN_COLOR12)
   1.326 +#define REG_COLOR13		REG(REGN_COLOR13)
   1.327 +#define REG_COLOR14		REG(REGN_COLOR14)
   1.328 +#define REG_COLOR15		REG(REGN_COLOR15)
   1.329 +#define REG_COLOR16		REG(REGN_COLOR16)
   1.330 +#define REG_COLOR17		REG(REGN_COLOR17)
   1.331 +#define REG_COLOR18		REG(REGN_COLOR18)
   1.332 +#define REG_COLOR19		REG(REGN_COLOR19)
   1.333 +#define REG_COLOR20		REG(REGN_COLOR20)
   1.334 +#define REG_COLOR21		REG(REGN_COLOR21)
   1.335 +#define REG_COLOR22		REG(REGN_COLOR22)
   1.336 +#define REG_COLOR23		REG(REGN_COLOR23)
   1.337 +#define REG_COLOR24		REG(REGN_COLOR24)
   1.338 +#define REG_COLOR25		REG(REGN_COLOR25)
   1.339 +#define REG_COLOR26		REG(REGN_COLOR26)
   1.340 +#define REG_COLOR27		REG(REGN_COLOR27)
   1.341 +#define REG_COLOR28		REG(REGN_COLOR28)
   1.342 +#define REG_COLOR29		REG(REGN_COLOR29)
   1.343 +#define REG_COLOR30		REG(REGN_COLOR30)
   1.344 +#define REG_COLOR31		REG(REGN_COLOR31)
   1.345 +
   1.346 +#define REG32_COP1LC	*(volatile uint32_t*)(REG_BASE_ADDR | REGN_COP1LCH)
   1.347 +#define REG32_COP2LC	*(volatile uint32_t*)(REG_BASE_ADDR | REGN_COP2LCH)
   1.348 +#define REG_COPJMP1		REG(REGN_COPJMP1)
   1.349 +#define REG_COPJMP2		REG(REGN_COPJMP2)
   1.350 +
   1.351 +/* ------ bits ------- */
   1.352 +#define SETBITS(x)	((x) | 0x8000)
   1.353 +#define CLRBITS(x)	(x)
   1.354 +
   1.355 +/* interrupt numbers */
   1.356 +enum {
   1.357 +	INTR_TBE,
   1.358 +	INTR_DSKBLK,
   1.359 +	INTR_SOFT,
   1.360 +	INTR_PORTS,
   1.361 +	INTR_COPPER,
   1.362 +	INTR_VERTB,
   1.363 +	INTR_BLITTER,
   1.364 +	INTR_AUDIO0,
   1.365 +	INTR_AUDIO1,
   1.366 +	INTR_AUDIO2,
   1.367 +	INTR_AUDIO3,
   1.368 +	INTR_RBF,
   1.369 +	INTR_DSKSYN,
   1.370 +	INTR_EXTER
   1.371 +};
   1.372 +
   1.373 +/* interrupt enable flags */
   1.374 +enum {
   1.375 +	INTEN_TBE		= 0x0001,
   1.376 +	INTEN_DSKBLK	= 0x0002,
   1.377 +	INTEN_SOFT		= 0x0004,
   1.378 +	INTEN_PORTS		= 0x0008,
   1.379 +	INTEN_COPPER	= 0x0010,
   1.380 +	INTEN_VERTB		= 0x0020,
   1.381 +	INTEN_BLITTER	= 0x0040,
   1.382 +	INTEN_AUDIO0	= 0x0080,
   1.383 +	INTEN_AUDIO1	= 0x0100,
   1.384 +	INTEN_AUDIO2	= 0x0200,
   1.385 +	INTEN_AUDIO3	= 0x0400,
   1.386 +	INTEN_RBF		= 0x0800,
   1.387 +	INTEN_DSKSYN	= 0x1000,
   1.388 +	INTEN_EXTER		= 0x2000,
   1.389 +	INTEN_MASTER	= 0x4000,
   1.390 +
   1.391 +	INTEN_ALL		= 0x7fff
   1.392 +};
   1.393 +
   1.394 +/* DMA control flags */
   1.395 +enum {
   1.396 +	DMA_AUD0		= 0x0001,
   1.397 +	DMA_AUD1		= 0x0002,
   1.398 +	DMA_AUD2		= 0x0004,
   1.399 +	DMA_AUD3		= 0x0008,
   1.400 +	DMA_AUDIO		= 0x000f,	/* all the above */
   1.401 +	DMA_DISK		= 0x0010,
   1.402 +	DMA_SPRITE		= 0x0020,
   1.403 +	DMA_BLITTER		= 0x0040,
   1.404 +	DMA_COPPER		= 0x0080,
   1.405 +	DMA_BPL			= 0x0100,
   1.406 +	DMA_MASTER		= 0x0200,
   1.407 +
   1.408 +	DMA_ALL			= 0x01ff
   1.409 +};
   1.410 +
   1.411 +/* Bitplane control */
   1.412 +enum {
   1.413 +	BPLCON0_ERSY	= 0x0002,
   1.414 +	BPLCON0_LACE	= 0x0004,
   1.415 +	BPLCON0_LPEN	= 0x0008,
   1.416 +	BPLCON0_GAUD	= 0x0100,
   1.417 +	BPLCON0_COLOR	= 0x0200,
   1.418 +	BPLCON0_DBLPF	= 0x0400,
   1.419 +	BPLCON0_HOMOD	= 0x0800,
   1.420 +	BPLCON0_BPU0	= 0x1000,
   1.421 +	BPLCON0_BPU1	= 0x2000,
   1.422 +	BPLCON0_BPU2	= 0x4000,
   1.423 +	BPLCON0_HIRES	= 0x8000
   1.424 +};
   1.425 +
   1.426 +#define BPLCON0_COUNT(x)	((x) << 12)
   1.427 +
   1.428 +#define CIAA_PA_FIR0	0x40
   1.429 +#define CIAA_PA_FIR1	0x80
   1.430 +
   1.431 +#endif	/* HWREGS_H_ */