oculus1: 402cbb6d9ce3 libovr/Src/Kernel/OVR

oculus1

view libovr/Src/Kernel/OVR_Atomic.h @ 15:402cbb6d9ce3

added the shader as a separate header file

author	John Tsiombikas <nuclear@member.fsf.org>
date	Sat, 21 Sep 2013 04:15:20 +0300
parents	e2f9e4603129
children

line source

1 /************************************************************************************

3 PublicHeader: OVR.h

4 Filename : OVR_Atomic.h

5 Content : Contains atomic operations and inline fastest locking

6 functionality. Will contain #ifdefs for OS efficiency.

7 Have non-thread-safe implementaion if not available.

8 Created : September 19, 2012

9 Notes :

13 Use of this software is subject to the terms of the Oculus license

14 agreement provided at the time of installation or download, or which

15 otherwise accompanies this software in either electronic or hard copy form.

17 ************************************************************************************/

18 #ifndef OVR_Atomic_h

19 #define OVR_Atomic_h

21 #include "OVR_Types.h"

23 // Include System thread functionality.

24 #if defined(OVR_OS_WIN32)

25 #include <windows.h>

26 #else

27 #include <pthread.h>

28 #endif

31 namespace OVR {

34 // ****** Declared classes

36 // If there is NO thread support we implement AtomicOps and

37 // Lock objects as no-ops. The other classes are not defined.

38 template<class C> class AtomicOps;

39 template<class T> class AtomicInt;

40 template<class T> class AtomicPtr;

42 class Lock;

45 //-----------------------------------------------------------------------------------

46 // ***** AtomicOps

48 // Atomic operations are provided by the AtomicOps templates class,

49 // implemented through system-specific AtomicOpsRaw specializations.

50 // It provides several fundamental operations such as Exchange, ExchangeAdd

51 // CompareAndSet, and Store_Release. Each function includes several memory

52 // synchronization versions, important for multiprocessing CPUs with weak

53 // memory consistency. The following memory fencing strategies are supported:

54 //

55 // - NoSync. No memory synchronization is done for atomic op.

56 // - Release. All other memory writes are completed before atomic op

57 // writes its results.

58 // - Acquire. Further memory reads are forced to wait until atomic op

59 // executes, guaranteeing that the right values will be seen.

60 // - Sync. A combination of Release and Acquire.

63 // *** AtomicOpsRaw

65 // AtomicOpsRaw is a specialized template that provides atomic operations

66 // used by AtomicOps. This class has two fundamental qualities: (1) it

67 // defines a type T of correct size, and (2) provides operations that work

68 // atomically, such as Exchange_Sync and CompareAndSet_Release.

70 // AtomicOpsRawBase class contains shared constants/classes for AtomicOpsRaw.

71 // The primary thing is does is define sync class objects, whose destructor and

72 // constructor provide places to insert appropriate synchronization calls, on

73 // systems where such calls are necessary. So far, the breakdown is as follows:

74 //

75 // - X86 systems don't need custom syncs, since their exchange/atomic

76 // instructions are implicitly synchronized.

77 // - PowerPC requires lwsync/isync instructions that can use this mechanism.

78 // - If some other systems require a mechanism where syncing type is associated

79 // with a particular instruction, the default implementation (which implements

80 // all Sync, Acquire, and Release modes in terms of NoSync and fence) may not

81 // work. Ii that case it will need to be #ifdef-ed conditionally.

83 struct AtomicOpsRawBase

84 {

85 #if !defined(OVR_ENABLE_THREADS) || defined(OVR_CPU_X86) || defined(OVR_OS_WIN32) || defined(OVR_OS_IPHONE)

86 // Need to have empty constructor to avoid class 'unused' variable warning.

87 struct FullSync { inline FullSync() { } };

88 struct AcquireSync { inline AcquireSync() { } };

89 struct ReleaseSync { inline ReleaseSync() { } };

91 #elif defined(OVR_CPU_PPC64) || defined(OVR_CPU_PPC)

92 struct FullSync { inline FullSync() { asm volatile("sync\n"); } ~FullSync() { asm volatile("isync\n"); } };

93 struct AcquireSync { inline AcquireSync() { } ~AcquireSync() { asm volatile("isync\n"); } };

94 struct ReleaseSync { inline ReleaseSync() { asm volatile("sync\n"); } };

96 #elif defined(OVR_CPU_MIPS)

97 struct FullSync { inline FullSync() { asm volatile("sync\n"); } ~FullSync() { asm volatile("sync\n"); } };

98 struct AcquireSync { inline AcquireSync() { } ~AcquireSync() { asm volatile("sync\n"); } };

99 struct ReleaseSync { inline ReleaseSync() { asm volatile("sync\n"); } };

100

101 #elif defined(OVR_CPU_ARM)

102 struct FullSync { inline FullSync() { asm volatile("dmb\n"); } ~FullSync() { asm volatile("dmb\n"); } };

103 struct AcquireSync { inline AcquireSync() { } ~AcquireSync() { asm volatile("dmb\n"); } };

104 struct ReleaseSync { inline ReleaseSync() { asm volatile("dmb\n"); } };

105

106

107 #elif defined(OVR_CC_GNU) && (__GNUC__ >= 4)

108 // __sync functions are already full sync

109 struct FullSync { inline FullSync() { } };

110 struct AcquireSync { inline AcquireSync() { } };

111 struct ReleaseSync { inline ReleaseSync() { } };

112 #endif

113 };

114

115

116 // 4-Byte raw data atomic op implementation class.

117 struct AtomicOpsRaw_4ByteImpl : public AtomicOpsRawBase

118 {

119 #if !defined(OVR_ENABLE_THREADS)

120

121 // Provide a type for no-thread-support cases. Used by AtomicOpsRaw_DefImpl.

122 typedef UInt32 T;

123

124 // *** Thread - Safe Atomic Versions.

125

126 #elif defined(OVR_OS_WIN32)

127

128 // Use special defined for VC6, where volatile is not used and

129 // InterlockedCompareExchange is declared incorrectly.

130 typedef LONG T;

131 #if defined(OVR_CC_MSVC) && (OVR_CC_MSVC < 1300)

132 typedef T* InterlockTPtr;

133 typedef LPVOID ET;

134 typedef ET* InterlockETPtr;

135 #else

136 typedef volatile T* InterlockTPtr;

137 typedef T ET;

138 typedef InterlockTPtr InterlockETPtr;

139 #endif

140 inline static T Exchange_NoSync(volatile T* p, T val) { return InterlockedExchange((InterlockTPtr)p, val); }

141 inline static T ExchangeAdd_NoSync(volatile T* p, T val) { return InterlockedExchangeAdd((InterlockTPtr)p, val); }

142 inline static bool CompareAndSet_NoSync(volatile T* p, T c, T val) { return InterlockedCompareExchange((InterlockETPtr)p, (ET)val, (ET)c) == (ET)c; }

143

144 #elif defined(OVR_CPU_PPC64) || defined(OVR_CPU_PPC)

145 typedef UInt32 T;

146 static inline UInt32 Exchange_NoSync(volatile UInt32 *i, UInt32 j)

147 {

148 UInt32 ret;

149

150 asm volatile("1:\n\t"

151 "lwarx %[r],0,%[i]\n\t"

152 "stwcx. %[j],0,%[i]\n\t"

153 "bne- 1b\n"

154 : "+m" (*i), [r] "=&b" (ret) : [i] "b" (i), [j] "b" (j) : "cc", "memory");

155

156 return ret;

157 }

158

159 static inline UInt32 ExchangeAdd_NoSync(volatile UInt32 *i, UInt32 j)

160 {

161 UInt32 dummy, ret;

162

163 asm volatile("1:\n\t"

164 "lwarx %[r],0,%[i]\n\t"

165 "add %[o],%[r],%[j]\n\t"

166 "stwcx. %[o],0,%[i]\n\t"

167 "bne- 1b\n"

168 : "+m" (*i), [r] "=&b" (ret), [o] "=&r" (dummy) : [i] "b" (i), [j] "b" (j) : "cc", "memory");

169

170 return ret;

171 }

172

173 static inline bool CompareAndSet_NoSync(volatile UInt32 *i, UInt32 c, UInt32 value)

174 {

175 UInt32 ret;

176

177 asm volatile("1:\n\t"

178 "lwarx %[r],0,%[i]\n\t"

179 "cmpw 0,%[r],%[cmp]\n\t"

180 "mfcr %[r]\n\t"

181 "bne- 2f\n\t"

182 "stwcx. %[val],0,%[i]\n\t"

183 "bne- 1b\n\t"

184 "2:\n"

185 : "+m" (*i), [r] "=&b" (ret) : [i] "b" (i), [cmp] "b" (c), [val] "b" (value) : "cc", "memory");

186

187 return (ret & 0x20000000) ? 1 : 0;

188 }

189

190 #elif defined(OVR_CPU_MIPS)

191 typedef UInt32 T;

192

193 static inline UInt32 Exchange_NoSync(volatile UInt32 *i, UInt32 j)

194 {

195 UInt32 ret;

196

197 asm volatile("1:\n\t"

198 "ll %[r],0(%[i])\n\t"

199 "sc %[j],0(%[i])\n\t"

200 "beq %[j],$0,1b\n\t"

201 "nop \n"

202 : "+m" (*i), [r] "=&d" (ret) : [i] "d" (i), [j] "d" (j) : "cc", "memory");

203

204 return ret;

205 }

206

207 static inline UInt32 ExchangeAdd_NoSync(volatile UInt32 *i, UInt32 j)

208 {

209 UInt32 ret;

210

211 asm volatile("1:\n\t"

212 "ll %[r],0(%[i])\n\t"

213 "addu %[j],%[r],%[j]\n\t"

214 "sc %[j],0(%[i])\n\t"

215 "beq %[j],$0,1b\n\t"

216 "nop \n"

217 : "+m" (*i), [r] "=&d" (ret) : [i] "d" (i), [j] "d" (j) : "cc", "memory");

218

219 return ret;

220 }

221

222 static inline bool CompareAndSet_NoSync(volatile UInt32 *i, UInt32 c, UInt32 value)

223 {

224 UInt32 ret, dummy;

225

226 asm volatile("1:\n\t"

227 "move %[r],$0\n\t"

228 "ll %[o],0(%[i])\n\t"

229 "bne %[o],%[c],2f\n\t"

230 "move %[r],%[v]\n\t"

231 "sc %[r],0(%[i])\n\t"

232 "beq %[r],$0,1b\n\t"

233 "nop \n\t"

234 "2:\n"

235 : "+m" (*i),[r] "=&d" (ret), [o] "=&d" (dummy) : [i] "d" (i), [c] "d" (c), [v] "d" (value)

236 : "cc", "memory");

237

238 return ret;

239 }

240

241 #elif defined(OVR_CPU_ARM) && defined(OVR_CC_ARM)

242 typedef UInt32 T;

243

244 static inline UInt32 Exchange_NoSync(volatile UInt32 *i, UInt32 j)

245 {

246 for(;;)

247 {

248 T r = __ldrex(i);

249 if (__strex(j, i) == 0)

250 return r;

251 }

252 }

253 static inline UInt32 ExchangeAdd_NoSync(volatile UInt32 *i, UInt32 j)

254 {

255 for(;;)

256 {

257 T r = __ldrex(i);

258 if (__strex(r + j, i) == 0)

259 return r;

260 }

261 }

262

263 static inline bool CompareAndSet_NoSync(volatile UInt32 *i, UInt32 c, UInt32 value)

264 {

265 for(;;)

266 {

267 T r = __ldrex(i);

268 if (r != c)

269 return 0;

270 if (__strex(value, i) == 0)

271 return 1;

272 }

273 }

274

275 #elif defined(OVR_CPU_ARM)

276 typedef UInt32 T;

277

278 static inline UInt32 Exchange_NoSync(volatile UInt32 *i, UInt32 j)

279 {

280 UInt32 ret, dummy;

281

282 asm volatile("1:\n\t"

283 "ldrex %[r],[%[i]]\n\t"

284 "strex %[t],%[j],[%[i]]\n\t"

285 "cmp %[t],#0\n\t"

286 "bne 1b\n\t"

287 : "+m" (*i), [r] "=&r" (ret), [t] "=&r" (dummy) : [i] "r" (i), [j] "r" (j) : "cc", "memory");

288

289 return ret;

290 }

291

292 static inline UInt32 ExchangeAdd_NoSync(volatile UInt32 *i, UInt32 j)

293 {

294 UInt32 ret, dummy, test;

295

296 asm volatile("1:\n\t"

297 "ldrex %[r],[%[i]]\n\t"

298 "add %[o],%[r],%[j]\n\t"

299 "strex %[t],%[o],[%[i]]\n\t"

300 "cmp %[t],#0\n\t"

301 "bne 1b\n\t"

302 : "+m" (*i), [r] "=&r" (ret), [o] "=&r" (dummy), [t] "=&r" (test) : [i] "r" (i), [j] "r" (j) : "cc", "memory");

303

304 return ret;

305 }

306

307 static inline bool CompareAndSet_NoSync(volatile UInt32 *i, UInt32 c, UInt32 value)

308 {

309 UInt32 ret = 1, dummy, test;

310

311 asm volatile("1:\n\t"

312 "ldrex %[o],[%[i]]\n\t"

313 "cmp %[o],%[c]\n\t"

314 "bne 2f\n\t"

315 "strex %[r],%[v],[%[i]]\n\t"

316 "cmp %[r],#0\n\t"

317 "bne 1b\n\t"

318 "2:\n"

319 : "+m" (*i),[r] "=&r" (ret), [o] "=&r" (dummy), [t] "=&r" (test) : [i] "r" (i), [c] "r" (c), [v] "r" (value)

320 : "cc", "memory");

321

322 return !ret;

323 }

324

325 #elif defined(OVR_CPU_X86)

326 typedef UInt32 T;

327

328 static inline UInt32 Exchange_NoSync(volatile UInt32 *i, UInt32 j)

329 {

330 asm volatile("xchgl %1,%[i]\n"

331 : "+m" (*i), "=q" (j) : [i] "m" (*i), "1" (j) : "cc", "memory");

332

333 return j;

334 }

335

336 static inline UInt32 ExchangeAdd_NoSync(volatile UInt32 *i, UInt32 j)

337 {

338 asm volatile("lock; xaddl %1,%[i]\n"

339 : "+m" (*i), "+q" (j) : [i] "m" (*i) : "cc", "memory");

340

341 return j;

342 }

343

344 static inline bool CompareAndSet_NoSync(volatile UInt32 *i, UInt32 c, UInt32 value)

345 {

346 UInt32 ret;

347

348 asm volatile("lock; cmpxchgl %[v],%[i]\n"

349 : "+m" (*i), "=a" (ret) : [i] "m" (*i), "1" (c), [v] "q" (value) : "cc", "memory");

350

351 return (ret == c);

352 }

353

354 #elif defined(OVR_CC_GNU) && (__GNUC__ >= 4 && __GNUC_MINOR__ >= 1)

355

356 typedef UInt32 T;

357

358 static inline T Exchange_NoSync(volatile T *i, T j)

359 {

360 T v;

361 do {

362 v = *i;

363 } while (!__sync_bool_compare_and_swap(i, v, j));

364 return v;

365 }

366

367 static inline T ExchangeAdd_NoSync(volatile T *i, T j)

368 {

369 return __sync_fetch_and_add(i, j);

370 }

371

372 static inline bool CompareAndSet_NoSync(volatile T *i, T c, T value)

373 {

374 return __sync_bool_compare_and_swap(i, c, value);

375 }

376

377 #endif // OS

378 };

379

380

381 // 8-Byte raw data data atomic op implementation class.

382 // Currently implementation is provided only on systems with 64-bit pointers.

383 struct AtomicOpsRaw_8ByteImpl : public AtomicOpsRawBase

384 {

385 #if !defined(OVR_64BIT_POINTERS) || !defined(OVR_ENABLE_THREADS)

386

387 // Provide a type for no-thread-support cases. Used by AtomicOpsRaw_DefImpl.

388 typedef UInt64 T;

389

390 // *** Thread - Safe OS specific versions.

391 #elif defined(OVR_OS_WIN32)

392

393 // This is only for 64-bit systems.

394 typedef LONG64 T;

395 typedef volatile T* InterlockTPtr;

396 inline static T Exchange_NoSync(volatile T* p, T val) { return InterlockedExchange64((InterlockTPtr)p, val); }

397 inline static T ExchangeAdd_NoSync(volatile T* p, T val) { return InterlockedExchangeAdd64((InterlockTPtr)p, val); }

398 inline static bool CompareAndSet_NoSync(volatile T* p, T c, T val) { return InterlockedCompareExchange64((InterlockTPtr)p, val, c) == c; }

399

400 #elif defined(OVR_CPU_PPC64)

401

402 typedef UInt64 T;

403

404 static inline UInt64 Exchange_NoSync(volatile UInt64 *i, UInt64 j)

405 {

406 UInt64 dummy, ret;

407

408 asm volatile("1:\n\t"

409 "ldarx %[r],0,%[i]\n\t"

410 "mr %[o],%[j]\n\t"

411 "stdcx. %[o],0,%[i]\n\t"

412 "bne- 1b\n"

413 : "+m" (*i), [r] "=&b" (ret), [o] "=&r" (dummy) : [i] "b" (i), [j] "b" (j) : "cc");

414

415 return ret;

416 }

417

418 static inline UInt64 ExchangeAdd_NoSync(volatile UInt64 *i, UInt64 j)

419 {

420 UInt64 dummy, ret;

421

422 asm volatile("1:\n\t"

423 "ldarx %[r],0,%[i]\n\t"

424 "add %[o],%[r],%[j]\n\t"

425 "stdcx. %[o],0,%[i]\n\t"

426 "bne- 1b\n"

427 : "+m" (*i), [r] "=&b" (ret), [o] "=&r" (dummy) : [i] "b" (i), [j] "b" (j) : "cc");

428

429 return ret;

430 }

431

432 static inline bool CompareAndSet_NoSync(volatile UInt64 *i, UInt64 c, UInt64 value)

433 {

434 UInt64 ret, dummy;

435

436 asm volatile("1:\n\t"

437 "ldarx %[r],0,%[i]\n\t"

438 "cmpw 0,%[r],%[cmp]\n\t"

439 "mfcr %[r]\n\t"

440 "bne- 2f\n\t"

441 "stdcx. %[val],0,%[i]\n\t"

442 "bne- 1b\n\t"

443 "2:\n"

444 : "+m" (*i), [r] "=&b" (ret), [o] "=&r" (dummy) : [i] "b" (i), [cmp] "b" (c), [val] "b" (value) : "cc");

445

446 return (ret & 0x20000000) ? 1 : 0;

447 }

448

449 #elif defined(OVR_CC_GNU) && (__GNUC__ >= 4 && __GNUC_MINOR__ >= 1)

450

451 typedef UInt64 T;

452

453 static inline T Exchange_NoSync(volatile T *i, T j)

454 {

455 T v;

456 do {

457 v = *i;

458 } while (!__sync_bool_compare_and_swap(i, v, j));

459 return v;

460 }

461

462 static inline T ExchangeAdd_NoSync(volatile T *i, T j)

463 {

464 return __sync_fetch_and_add(i, j);

465 }

466

467 static inline bool CompareAndSet_NoSync(volatile T *i, T c, T value)

468 {

469 return __sync_bool_compare_and_swap(i, c, value);

470 }

471

472 #endif // OS

473 };

474

475

476 // Default implementation for AtomicOpsRaw; provides implementation of mem-fenced

477 // atomic operations where fencing is done with a sync object wrapped around a NoSync

478 // operation implemented in the base class. If such implementation is not possible

479 // on a given platform, #ifdefs can be used to disable it and then op functions can be

480 // implemented individually in the appropriate AtomicOpsRaw<size> class.

481

482 template<class O>

483 struct AtomicOpsRaw_DefImpl : public O

484 {

485 typedef typename O::T O_T;

486 typedef typename O::FullSync O_FullSync;

487 typedef typename O::AcquireSync O_AcquireSync;

488 typedef typename O::ReleaseSync O_ReleaseSync;

489

490 // If there is no thread support, provide the default implementation. In this case,

491 // the base class (0) must still provide the T declaration.

492 #ifndef OVR_ENABLE_THREADS

493

494 // Atomic exchange of val with argument. Returns old val.

495 inline static O_T Exchange_NoSync(volatile O_T* p, O_T val) { O_T old = *p; *p = val; return old; }

496 // Adds a new val to argument; returns its old val.

497 inline static O_T ExchangeAdd_NoSync(volatile O_T* p, O_T val) { O_T old = *p; *p += val; return old; }

498 // Compares the argument data with 'c' val.

499 // If succeeded, stores val int '*p' and returns true; otherwise returns false.

500 inline static bool CompareAndSet_NoSync(volatile O_T* p, O_T c, O_T val) { if (*p==c) { *p = val; return 1; } return 0; }

501

502 #endif

503

504 // If NoSync wrapped implementation may not be possible, it this block should be

505 // replaced with per-function implementation in O.

506 // "AtomicOpsRaw_DefImpl<O>::" prefix in calls below.

507 inline static O_T Exchange_Sync(volatile O_T* p, O_T val) { O_FullSync sync; OVR_UNUSED(sync); return AtomicOpsRaw_DefImpl<O>::Exchange_NoSync(p, val); }

508 inline static O_T Exchange_Release(volatile O_T* p, O_T val) { O_ReleaseSync sync; OVR_UNUSED(sync); return AtomicOpsRaw_DefImpl<O>::Exchange_NoSync(p, val); }

509 inline static O_T Exchange_Acquire(volatile O_T* p, O_T val) { O_AcquireSync sync; OVR_UNUSED(sync); return AtomicOpsRaw_DefImpl<O>::Exchange_NoSync(p, val); }

510 inline static O_T ExchangeAdd_Sync(volatile O_T* p, O_T val) { O_FullSync sync; OVR_UNUSED(sync); return AtomicOpsRaw_DefImpl<O>::ExchangeAdd_NoSync(p, val); }

511 inline static O_T ExchangeAdd_Release(volatile O_T* p, O_T val) { O_ReleaseSync sync; OVR_UNUSED(sync); return AtomicOpsRaw_DefImpl<O>::ExchangeAdd_NoSync(p, val); }

512 inline static O_T ExchangeAdd_Acquire(volatile O_T* p, O_T val) { O_AcquireSync sync; OVR_UNUSED(sync); return AtomicOpsRaw_DefImpl<O>::ExchangeAdd_NoSync(p, val); }

513 inline static bool CompareAndSet_Sync(volatile O_T* p, O_T c, O_T val) { O_FullSync sync; OVR_UNUSED(sync); return AtomicOpsRaw_DefImpl<O>::CompareAndSet_NoSync(p,c,val); }

514 inline static bool CompareAndSet_Release(volatile O_T* p, O_T c, O_T val) { O_ReleaseSync sync; OVR_UNUSED(sync); return AtomicOpsRaw_DefImpl<O>::CompareAndSet_NoSync(p,c,val); }

515 inline static bool CompareAndSet_Acquire(volatile O_T* p, O_T c, O_T val) { O_AcquireSync sync; OVR_UNUSED(sync); return AtomicOpsRaw_DefImpl<O>::CompareAndSet_NoSync(p,c,val); }

516

517 // Loads and stores with memory fence. These have only the relevant versions.

518 #ifdef OVR_CPU_X86

519 // On X86, Store_Release is implemented as exchange. Note that we can also

520 // consider 'sfence' in the future, although it is not as compatible with older CPUs.

521 inline static void Store_Release(volatile O_T* p, O_T val) { Exchange_Release(p, val); }

522 #else

523 inline static void Store_Release(volatile O_T* p, O_T val) { O_ReleaseSync sync; OVR_UNUSED(sync); *p = val; }

524 #endif

525 inline static O_T Load_Acquire(const volatile O_T* p) { O_AcquireSync sync; OVR_UNUSED(sync); return *p; }

526 };

527

528

529 template<int size>

530 struct AtomicOpsRaw : public AtomicOpsRawBase { };

531

532 template<>

533 struct AtomicOpsRaw<4> : public AtomicOpsRaw_DefImpl<AtomicOpsRaw_4ByteImpl>

534 {

535 // Ensure that assigned type size is correct.

536 AtomicOpsRaw()

537 { OVR_COMPILER_ASSERT(sizeof(AtomicOpsRaw_DefImpl<AtomicOpsRaw_4ByteImpl>::T) == 4); }

538 };

539 template<>

540 struct AtomicOpsRaw<8> : public AtomicOpsRaw_DefImpl<AtomicOpsRaw_8ByteImpl>

541 {

542 AtomicOpsRaw()

543 { OVR_COMPILER_ASSERT(sizeof(AtomicOpsRaw_DefImpl<AtomicOpsRaw_8ByteImpl>::T) == 8); }

544 };

545

546

547 // *** AtomicOps - implementation of atomic Ops for specified class

548

549 // Implements atomic ops on a class, provided that the object is either

550 // 4 or 8 bytes in size (depending on the AtomicOpsRaw specializations

551 // available). Relies on AtomicOpsRaw for much of implementation.

552

553 template<class C>

554 class AtomicOps

555 {

556 typedef AtomicOpsRaw<sizeof(C)> Ops;

557 typedef typename Ops::T T;

558 typedef volatile typename Ops::T* PT;

559 // We cast through unions to (1) avoid pointer size compiler warnings

560 // and (2) ensure that there are no problems with strict pointer aliasing.

561 union C2T_union { C c; T t; };

562

563 public:

564 // General purpose implementation for standard syncs.

565 inline static C Exchange_Sync(volatile C* p, C val) { C2T_union u; u.c = val; u.t = Ops::Exchange_Sync((PT)p, u.t); return u.c; }

566 inline static C Exchange_Release(volatile C* p, C val) { C2T_union u; u.c = val; u.t = Ops::Exchange_Release((PT)p, u.t); return u.c; }

567 inline static C Exchange_Acquire(volatile C* p, C val) { C2T_union u; u.c = val; u.t = Ops::Exchange_Acquire((PT)p, u.t); return u.c; }

568 inline static C Exchange_NoSync(volatile C* p, C val) { C2T_union u; u.c = val; u.t = Ops::Exchange_NoSync((PT)p, u.t); return u.c; }

569 inline static C ExchangeAdd_Sync(volatile C* p, C val) { C2T_union u; u.c = val; u.t = Ops::ExchangeAdd_Sync((PT)p, u.t); return u.c; }

570 inline static C ExchangeAdd_Release(volatile C* p, C val) { C2T_union u; u.c = val; u.t = Ops::ExchangeAdd_Release((PT)p, u.t); return u.c; }

571 inline static C ExchangeAdd_Acquire(volatile C* p, C val) { C2T_union u; u.c = val; u.t = Ops::ExchangeAdd_Acquire((PT)p, u.t); return u.c; }

572 inline static C ExchangeAdd_NoSync(volatile C* p, C val) { C2T_union u; u.c = val; u.t = Ops::ExchangeAdd_NoSync((PT)p, u.t); return u.c; }

573 inline static bool CompareAndSet_Sync(volatile C* p, C c, C val) { C2T_union u,cu; u.c = val; cu.c = c; return Ops::CompareAndSet_Sync((PT)p, cu.t, u.t); }

574 inline static bool CompareAndSet_Release(volatile C* p, C c, C val){ C2T_union u,cu; u.c = val; cu.c = c; return Ops::CompareAndSet_Release((PT)p, cu.t, u.t); }

575 inline static bool CompareAndSet_Relse(volatile C* p, C c, C val){ C2T_union u,cu; u.c = val; cu.c = c; return Ops::CompareAndSet_Acquire((PT)p, cu.t, u.t); }

576 inline static bool CompareAndSet_NoSync(volatile C* p, C c, C val) { C2T_union u,cu; u.c = val; cu.c = c; return Ops::CompareAndSet_NoSync((PT)p, cu.t, u.t); }

577 // Loads and stores with memory fence. These have only the relevant versions.

578 inline static void Store_Release(volatile C* p, C val) { C2T_union u; u.c = val; Ops::Store_Release((PT)p, u.t); }

579 inline static C Load_Acquire(const volatile C* p) { C2T_union u; u.t = Ops::Load_Acquire((PT)p); return u.c; }

580 };

581

582

583

584 // Atomic value base class - implements operations shared for integers and pointers.

585 template<class T>

586 class AtomicValueBase

587 {

588 protected: