nds_test1
diff src/startup/mpu_setup.S @ 0:ab2afb70001a
initial commit test1 without libnds
author | John Tsiombikas <nuclear@member.fsf.org> |
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date | Sat, 27 Jan 2018 23:38:00 +0200 |
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children |
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1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 1.2 +++ b/src/startup/mpu_setup.S Sat Jan 27 23:38:00 2018 +0200 1.3 @@ -0,0 +1,203 @@ 1.4 +@ vi:set filetype=armasm: 1.5 +#define PAGE_4K (0b01011 << 1) 1.6 +#define PAGE_8K (0b01100 << 1) 1.7 +#define PAGE_16K (0b01101 << 1) 1.8 +#define PAGE_32K (0b01110 << 1) 1.9 +#define PAGE_64K (0b01111 << 1) 1.10 +#define PAGE_128K (0b10000 << 1) 1.11 +#define PAGE_256K (0b10001 << 1) 1.12 +#define PAGE_512K (0b10010 << 1) 1.13 +#define PAGE_1M (0b10011 << 1) 1.14 +#define PAGE_2M (0b10100 << 1) 1.15 +#define PAGE_4M (0b10101 << 1) 1.16 +#define PAGE_8M (0b10110 << 1) 1.17 +#define PAGE_16M (0b10111 << 1) 1.18 +#define PAGE_32M (0b11000 << 1) 1.19 +#define PAGE_64M (0b11001 << 1) 1.20 +#define PAGE_128M (0b11010 << 1) 1.21 +#define PAGE_256M (0b11011 << 1) 1.22 +#define PAGE_512M (0b11100 << 1) 1.23 +#define PAGE_1G (0b11101 << 1) 1.24 +#define PAGE_2G (0b11110 << 1) 1.25 +#define PAGE_4G (0b11111 << 1) 1.26 + 1.27 +#define ITCM_LOAD (1<<19) 1.28 +#define ITCM_ENABLE (1<<18) 1.29 +#define DTCM_LOAD (1<<17) 1.30 +#define DTCM_ENABLE (1<<16) 1.31 +#define DISABLE_TBIT (1<<15) 1.32 +#define ROUND_ROBIN (1<<14) 1.33 +#define ALT_VECTORS (1<<13) 1.34 +#define ICACHE_ENABLE (1<<12) 1.35 +#define BIG_ENDIAN (1<<7) 1.36 +#define DCACHE_ENABLE (1<<2) 1.37 +#define PROTECT_ENABLE (1<<0) 1.38 + 1.39 + .arch armv5te 1.40 + .cpu arm946e-s 1.41 + 1.42 + .text 1.43 + .arm 1.44 + 1.45 + .global mpu_setup 1.46 + .align 2 1.47 +mpu_setup: 1.48 +@ turn the power on for M3 1.49 + ldr r1, =0x8203 1.50 + mov r0, #0x04000000 1.51 + add r0, r0, #0x304 1.52 + strh r1, [r0] 1.53 + 1.54 + ldr r1, =0x00002078 @ disable TCM and protection unit 1.55 + mcr p15, 0, r1, c1, c0 1.56 + 1.57 +@ Protection Unit Setup added by Sasq 1.58 + @ Disable cache 1.59 + mov r0, #0 1.60 + mcr p15, 0, r0, c7, c5, 0 @ Instruction cache 1.61 + mcr p15, 0, r0, c7, c6, 0 @ Data cache 1.62 + 1.63 + @ Wait for write buffer to empty 1.64 + mcr p15, 0, r0, c7, c10, 4 1.65 + 1.66 + ldr r0, =__dtcm_start 1.67 + orr r0,r0,#0x0a 1.68 + mcr p15, 0, r0, c9, c1,0 @ DTCM base = __dtcm_start, size = 16 KB 1.69 + 1.70 + mov r0,#0x20 1.71 + mcr p15, 0, r0, c9, c1,1 @ ITCM base = 0 , size = 32 MB 1.72 + 1.73 +@ Setup memory regions similar to Release Version 1.74 + @ Region 0 - IO registers 1.75 + ldr r0,=( PAGE_64M | 0x04000000 | 1) 1.76 + mcr p15, 0, r0, c6, c0, 0 1.77 + 1.78 + @ Region 1 - System ROM 1.79 + ldr r0,=( PAGE_64K | 0xFFFF0000 | 1) 1.80 + mcr p15, 0, r0, c6, c1, 0 1.81 + 1.82 + @ Region 2 - alternate vector base 1.83 + ldr r0,=( PAGE_4K | 0x00000000 | 1) 1.84 + mcr p15, 0, r0, c6, c2, 0 1.85 + 1.86 + @ Region 5 - DTCM 1.87 + ldr r0,=__dtcm_start 1.88 + orr r0,r0,#(PAGE_16K | 1) 1.89 + mcr p15, 0, r0, c6, c5, 0 1.90 + 1.91 + @ Region 4 - ITCM 1.92 + ldr r0,=__itcm_start 1.93 + 1.94 + @ align to 32k boundary 1.95 + mov r0,r0,lsr #15 1.96 + mov r0,r0,lsl #15 1.97 + 1.98 + orr r0,r0,#(PAGE_32K | 1) 1.99 + mcr p15, 0, r0, c6, c4, 0 1.100 + 1.101 + ldr r0,=0x4004008 1.102 + ldr r0,[r0] 1.103 + tst r0,#0x8000 1.104 + bne dsi_mode 1.105 + 1.106 + swi 0xf0000 1.107 + 1.108 + ldr r1,=( PAGE_128M | 0x08000000 | 1) 1.109 + cmp r0,#0 1.110 + bne debug_mode 1.111 + 1.112 + ldr r3,=( PAGE_4M | 0x02000000 | 1) 1.113 + ldr r2,=( PAGE_16M | 0x02000000 | 1) 1.114 + mov r8,#0x02400000 1.115 + 1.116 + ldr r9,=dsmasks 1.117 + b setregions 1.118 + 1.119 +debug_mode: 1.120 + ldr r3,=( PAGE_8M | 0x02000000 | 1) 1.121 + ldr r2,=( PAGE_8M | 0x02800000 | 1) 1.122 + mov r8,#0x02800000 1.123 + ldr r9,=debugmasks 1.124 + b setregions 1.125 + 1.126 +dsi_mode: 1.127 + tst r0,#0x4000 1.128 + ldr r1,=( PAGE_8M | 0x03000000 | 1) 1.129 + ldr r3,=( PAGE_16M | 0x02000000 | 1) 1.130 + ldreq r2,=( PAGE_16M | 0x0C000000 | 1) 1.131 + ldrne r2,=( PAGE_32M | 0x0C000000 | 1) @ DSi debugger extended iwram 1.132 + mov r8,#0x03000000 1.133 + ldr r9,=dsimasks 1.134 + 1.135 +setregions: 1.136 + @ Region 3 - DS Accessory (GBA Cart) / DSi switchable iwram 1.137 + mcr p15, 0, r1, c6, c3, 0 1.138 + 1.139 + @ Region 6 - non cacheable main ram 1.140 + mcr p15, 0, r2, c6, c6, 0 1.141 + 1.142 + @ Region 7 - cacheable main ram 1.143 + mcr p15, 0, r3, c6, c7, 0 1.144 + 1.145 + 1.146 + @ Write buffer enable 1.147 + ldr r0,=0b10000000 1.148 + mcr p15, 0, r0, c3, c0, 0 1.149 + 1.150 + @ DCache & ICache enable 1.151 + ldr r0,=0b10000010 1.152 + mcr p15, 0, r0, c2, c0, 0 1.153 + mcr p15, 0, r0, c2, c0, 1 1.154 + 1.155 + @ IAccess 1.156 + ldr r0,=0x33333363 1.157 + mcr p15, 0, r0, c5, c0, 3 1.158 + 1.159 + @ DAccess 1.160 + mcr p15, 0, r0, c5, c0, 2 1.161 + 1.162 + @ Enable ICache, DCache, ITCM & DTCM 1.163 + mrc p15, 0, r0, c1, c0, 0 1.164 + ldr r1,= ITCM_ENABLE | DTCM_ENABLE | ICACHE_ENABLE | DCACHE_ENABLE | PROTECT_ENABLE 1.165 + orr r0,r0,r1 1.166 + mcr p15, 0, r0, c1, c0, 0 1.167 + 1.168 + ldr r0,=masks 1.169 + str r9,[r0] 1.170 + 1.171 + bx lr 1.172 + 1.173 + .global memCached 1.174 + .align 2 1.175 +memCached: 1.176 + ldr r1,=masks 1.177 + ldr r1, [r1] 1.178 + ldr r2,[r1],#4 1.179 + and r0,r0,r2 1.180 + ldr r2,[r1] 1.181 + orr r0,r0,r2 1.182 + bx lr 1.183 + 1.184 + .global memUncached 1.185 + .align 2 1.186 +memUncached: 1.187 + ldr r1,=masks 1.188 + ldr r1, [r1] 1.189 + ldr r2,[r1],#8 1.190 + and r0,r0,r2 1.191 + ldr r2,[r1] 1.192 + orr r0,r0,r2 1.193 + bx lr 1.194 + 1.195 + .data 1.196 + .align 2 1.197 + 1.198 +dsmasks: 1.199 + .word 0x003fffff, 0x02000000, 0x02c00000 1.200 +debugmasks: 1.201 + .word 0x007fffff, 0x02000000, 0x02800000 1.202 +dsimasks: 1.203 + .word 0x00ffffff, 0x02000000, 0x0c000000 1.204 + 1.205 +masks: .word dsmasks 1.206 +