nuclear@1: #include <stdint.h>
nuclear@0: #include "vdp.h"
nuclear@6: #include "io.h"
nuclear@9: #include "pad.h"
nuclear@9: #include "intr.h"
nuclear@5: #include "tun_data.h"
nuclear@0: 
nuclear@5: #define NAMETAB_A	6
nuclear@5: #define NAMETAB_B	6
nuclear@5: 
nuclear@5: void load_pattern(int idx, void *data);
nuclear@5: void set_tile(int nametab_idx, int x, int y, int tile_idx, int palidx);
nuclear@5: 
nuclear@5: #define CYCLE_BEG	1
nuclear@5: #define CYCLE_END	14
nuclear@5: static uint16_t pal[16] = {
nuclear@5: 	VDP_PACK_RGB(0, 0, 0),	/* 0: fixed */
nuclear@5: 	VDP_PACK_RGB(0, 0, 0),	/* 1: cycle start */
nuclear@5: 	VDP_PACK_RGB(0, 0, 0), VDP_PACK_RGB(0, 0, 0),
nuclear@5: 	VDP_PACK_RGB(0, 0, 0), VDP_PACK_RGB(0, 0, 0),
nuclear@5: 	VDP_PACK_RGB(0, 0, 0), VDP_PACK_RGB(0, 0, 0),
nuclear@5: 	VDP_PACK_RGB(0, 0, 0), VDP_PACK_RGB(0, 0, 0),
nuclear@5: 	VDP_PACK_RGB(0, 0, 0), VDP_PACK_RGB(0, 0, 0),
nuclear@5: 	VDP_PACK_RGB(0, 0, 0),	/* 12: \            */
nuclear@5: 	VDP_PACK_RGB(7, 0, 3),	/* 13:  > beam      */
nuclear@5: 	VDP_PACK_RGB(0, 0, 0),	/* 14: /  cycle end */
nuclear@5: 	VDP_PACK_RGB(7, 0, 3)		/* 15: fixed */
nuclear@4: };
nuclear@4: 
nuclear@4: 
nuclear@0: int main(void)
nuclear@0: {
nuclear@4: 	int i, j;
nuclear@4: 
nuclear@0: 	vdp_init();
nuclear@0: 
nuclear@6: 	if(IO_REG_VER & IO_VER_PAL) {
nuclear@6: 		vdp_setreg(VDP_REG_MODE2, vdp_getreg(VDP_REG_MODE2) | VDP_MODE2_V30CELL);
nuclear@6: 	}
nuclear@5: 
nuclear@5: 	vdp_begin_palette(0, 0);
nuclear@5: 	for(i=0; i<16; i++) {
nuclear@5: 		VDP_PORT_DATA = pal[i];
nuclear@5: 	}
nuclear@0: 
nuclear@5: 	for(i=0; i<tun_xtiles * tun_ytiles; i++) {
nuclear@5: 		load_pattern(i, tun_tiles[i]);
nuclear@5: 	}
nuclear@4: 
nuclear@5: 	vdp_set_nametab_idx(VDP_PLANE_A, NAMETAB_A);
nuclear@5: 	vdp_set_nametab_idx(VDP_PLANE_B, NAMETAB_B);
nuclear@4: 
nuclear@5: 	for(i=0; i<tun_ytiles; i++) {
nuclear@5: 		for(j=0; j<tun_xtiles; j++) {
nuclear@5: 			set_tile(NAMETAB_A, j, i, i * tun_xtiles + j, 0);
nuclear@4: 		}
nuclear@4: 	}
nuclear@4: 
nuclear@4: 	//vdp_enable_hintr(12);
nuclear@5: 	vdp_enable_vintr();
nuclear@1: 
nuclear@8: 	for(;;) {
nuclear@9: 		pad_update(0);
nuclear@8: 
nuclear@9: 		if(pad_pressed(0, IO_PAD_C)) {
nuclear@9: 			disable_intr();
nuclear@9: 			vdp_setreg(VDP_REG_MODE2, vdp_getreg(VDP_REG_MODE2) ^ VDP_MODE2_V30CELL);
nuclear@9: 			enable_intr();
nuclear@8: 		}
nuclear@8: 
nuclear@8: 		vdp_wait_vblank();
nuclear@8: 	}
nuclear@0: 
nuclear@0: 	return 0;
nuclear@0: }
nuclear@1: 
nuclear@4: void load_pattern(int idx, void *data)
nuclear@4: {
nuclear@4: 	int i;
nuclear@4: 	uint32_t *ptr = data;
nuclear@4: 	uint16_t addr = idx << 5;
nuclear@4: 	vdp_setup_access(addr, VDP_MEM_WRITE, VDP_MEM_VRAM);
nuclear@4: 
nuclear@4: 	for(i=0; i<16; i++) {
nuclear@4: 		VDP_PORT_DATA32 = *ptr++;
nuclear@4: 	}
nuclear@4: }
nuclear@4: 
nuclear@5: void set_tile(int nametab_idx, int x, int y, int tile_idx, int palidx)
nuclear@4: {
nuclear@4: 	uint16_t tile_ent, addr;
nuclear@4: 
nuclear@4: 	tile_ent = vdp_nametab_entry(tile_idx, palidx, VDP_TILE_LOW_PRIO);
nuclear@4: 
nuclear@5: 	addr = vdp_nametab_addr(nametab_idx) + (y * 64 + x) * 2;
nuclear@4: 	vdp_setup_access(addr, VDP_MEM_WRITE, VDP_MEM_VRAM);
nuclear@4: 	VDP_PORT_DATA = tile_ent;
nuclear@4: }
nuclear@5: 
nuclear@5: void vblank_handler(void)
nuclear@5: {
nuclear@5: 	int idx = CYCLE_BEG;
nuclear@8: 	uint16_t first;
nuclear@8: 
nuclear@8: 	first = pal[idx];
nuclear@5: 
nuclear@5: 	vdp_begin_palette(0, idx);
nuclear@5: 	while(idx < CYCLE_END) {
nuclear@5: 		pal[idx] = pal[idx + 1];
nuclear@5: 		VDP_PORT_DATA = pal[idx];
nuclear@5: 		++idx;
nuclear@5: 	}
nuclear@5: 	pal[idx] = first;
nuclear@5: 	VDP_PORT_DATA = pal[idx];
nuclear@5: }