megadrive_test2

view src/intr.s @ 5:ea70f3da150f

find changesets by author, revision, files, or words in the commit message
color cycling tunnel
author John Tsiombikas <nuclear@member.fsf.org>
date Tue, 20 Jun 2017 06:08:58 +0300
parents 72ab63f262bf
children
line source
1 | vi:filetype=gas68k:
2 | the following will go into the .vect section which will be placed at the very
3 | begining of the binary at address 0 by the linker (see lnkscript).
4 .section .vect,"a"
5 .extern start
6 | exception vectors
7 .long _stacktop | 00 reset - initial SSP
8 .long start | 01 reset - initial PC
9 .long intr_fatal | 02 bus error
10 .long intr_fatal | 03 address error
11 .long intr_fatal | 04 illegal instruction
12 .long intr_fatal | 05 zero divide
13 .long intr_fatal | 06 chk instruction
14 .long intr_fatal | 07 trapv instruction
15 .long intr_fatal | 08 privilege violation
16 .long intr_fatal | 09 trace
17 .long intr_fatal | 0a line 1010 emulator
18 .long intr_fatal | 0b line 1111 emulator
19 .long intr_fatal | 0c reserved
20 .long intr_fatal | 0d reserved
21 .long intr_fatal | 0e format error (mc68010 only)
22 .long intr_fatal | 0f uninitialized interrupt vector
23 .long intr_fatal | 10 \
24 .long intr_fatal | 11 |
25 .long intr_fatal | 12 |
26 .long intr_fatal | 13 > reserved
27 .long intr_fatal | 14 |
28 .long intr_fatal | 15 |
29 .long intr_fatal | 16 |
30 .long intr_fatal | 17 /
31 .long intr_fatal | 18 spurious interrupt
32 .long intr_fatal | 19 level 1 interrupt
33 .long intr_fatal | 1a level 2 interrupt
34 .long intr_fatal | 1b level 3 interrupt
35 .long intr_hblank | 1c level 4 interrupt (hblank in the mega drive)
36 .long intr_fatal | 1d level 5 interrupt
37 .long intr_vblank | 1e level 6 interrupt (vblank in the mega drive)
38 .long intr_fatal | 1f level 7 interrupt
39 .long intr_fatal | 20 trap 0
40 .long intr_fatal | 21 trap 1
41 .long intr_fatal | 22 trap 2
42 .long intr_fatal | 23 trap 3
43 .long intr_fatal | 24 trap 4
44 .long intr_fatal | 25 trap 5
45 .long intr_fatal | 26 trap 6
46 .long intr_fatal | 27 trap 7
47 .long intr_fatal | 28 trap 8
48 .long intr_fatal | 29 trap 9
49 .long intr_fatal | 2a trap a
50 .long intr_fatal | 2b trap b
51 .long intr_fatal | 2c trap c
52 .long intr_fatal | 2d trap d
53 .long intr_fatal | 2e trap e
54 .long intr_fatal | 2f trap f
55 .long intr_fatal | 30 \
56 .long intr_fatal | 31 |
57 .long intr_fatal | 32 |
58 .long intr_fatal | 33 |
59 .long intr_fatal | 34 |
60 .long intr_fatal | 35 |
61 .long intr_fatal | 36 |
62 .long intr_fatal | 37 |
63 .long intr_fatal | 38 > reserved
64 .long intr_fatal | 39 |
65 .long intr_fatal | 3a |
66 .long intr_fatal | 3b |
67 .long intr_fatal | 3c |
68 .long intr_fatal | 3d |
69 .long intr_fatal | 3e |
70 .long intr_fatal | 3f /
71
72 | from here on we continue in the regular .text section since we don't care
73 | where this code ends up.
74 .text
75
76 .global enable_intr
77 enable_intr:
78 andi.w #0xf8ff, %sr
79 rts
80
81 .global disable_intr
82 disable_intr:
83 ori.w #0x0300, %sr
84 rts
85
86 | interrupt handlers
87 intr_fatal:
88 stop #0x2700
89
90 .include "vdpdefs.inc"
91 .extern vblank_handler
92 .extern palval
93
94 intr_hblank:
95 | move.l #0xc0020000, VDP_PORT_CTL
96 |
97 | move.w testcol, %d0
98 | move.w %d0, VDP_PORT_DATA
99 | rol.b #4, %d0
100 | move.w %d0, testcol
101 |
102 rte
103
104 intr_vblank:
105 jsr vblank_handler
106 rte