1.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.2 +++ b/src/desc.h	Sat Feb 19 04:41:51 2011 +0200
     1.3 @@ -0,0 +1,10 @@
     1.4 +#ifndef DESC_H_
     1.5 +#define DESC_H_
     1.6 +
     1.7 +#include <inttypes.h>
     1.8 +
     1.9 +typedef struct {
    1.10 +	uint16_t d[4];
    1.11 +} desc_t;
    1.12 +
    1.13 +#endif	/* DESC_H_ */

     2.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     2.2 +++ b/src/interrupts.h	Sat Feb 19 04:41:51 2011 +0200
     2.3 @@ -0,0 +1,54 @@
     2.4 +#ifdef ASM
     2.5 +/* included from intr-asm.S */
     2.6 +#define INTR_ENTRY_EC(n, name)		ientry_err n, name
     2.7 +#define INTR_ENTRY_NOEC(n, name)	ientry_noerr n, name
     2.8 +#else
     2.9 +/* included from intr.c inside init_intr() */
    2.10 +#define INTR_ENTRY_EC(n, name)		\
    2.11 +	void intr_entry_##name(void);	\
    2.12 +	set_intr_entry(n, intr_entry_##name);
    2.13 +#define INTR_ENTRY_NOEC(n, name)	INTR_ENTRY_EC(n, name)
    2.14 +#endif	/* ASM */
    2.15 +
    2.16 +/* faults/traps/aborts (plus NMI) */
    2.17 +INTR_ENTRY_NOEC(0, div)
    2.18 +INTR_ENTRY_NOEC(1, debug)
    2.19 +INTR_ENTRY_NOEC(2, nmi)
    2.20 +INTR_ENTRY_NOEC(3, bp)
    2.21 +INTR_ENTRY_NOEC(4, overflow)
    2.22 +INTR_ENTRY_NOEC(5, bound)
    2.23 +INTR_ENTRY_NOEC(6, ill)
    2.24 +INTR_ENTRY_NOEC(7, nodev)
    2.25 +INTR_ENTRY_EC(8, dfault)
    2.26 +INTR_ENTRY_NOEC(9, copseg)
    2.27 +INTR_ENTRY_EC(10, tss)
    2.28 +INTR_ENTRY_EC(11, segpres)
    2.29 +INTR_ENTRY_EC(12, stack)
    2.30 +INTR_ENTRY_EC(13, prot)
    2.31 +INTR_ENTRY_EC(14, page)
    2.32 +INTR_ENTRY_NOEC(15, reserved)
    2.33 +INTR_ENTRY_NOEC(16, fpu)
    2.34 +INTR_ENTRY_EC(17, align)
    2.35 +INTR_ENTRY_NOEC(18, mce)
    2.36 +INTR_ENTRY_NOEC(19, sse)
    2.37 +/* redirected IRQs */
    2.38 +INTR_ENTRY_NOEC(32, irq0)
    2.39 +INTR_ENTRY_NOEC(33, irq1)
    2.40 +INTR_ENTRY_NOEC(34, irq2)
    2.41 +INTR_ENTRY_NOEC(35, irq3)
    2.42 +INTR_ENTRY_NOEC(36, irq4)
    2.43 +INTR_ENTRY_NOEC(37, irq5)
    2.44 +INTR_ENTRY_NOEC(38, irq6)
    2.45 +INTR_ENTRY_NOEC(39, irq7)
    2.46 +INTR_ENTRY_NOEC(40, irq8)
    2.47 +INTR_ENTRY_NOEC(41, irq9)
    2.48 +INTR_ENTRY_NOEC(42, irq10)
    2.49 +INTR_ENTRY_NOEC(43, irq11)
    2.50 +INTR_ENTRY_NOEC(44, irq12)
    2.51 +INTR_ENTRY_NOEC(45, irq13)
    2.52 +INTR_ENTRY_NOEC(46, irq14)
    2.53 +INTR_ENTRY_NOEC(47, irq15)
    2.54 +/* system call interrupt */
    2.55 +INTR_ENTRY_NOEC(128, syscall)
    2.56 +/* default interrupt */
    2.57 +INTR_ENTRY_NOEC(255, default)

     3.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     3.2 +++ b/src/intr-asm.S	Sat Feb 19 04:41:51 2011 +0200
     3.3 @@ -0,0 +1,60 @@
     3.4 +	.data
     3.5 +	.align 4
     3.6 +	.short 0
     3.7 +/* memory reserved for set_idt */
     3.8 +lim:.short 0
     3.9 +addr:.long 0
    3.10 +
    3.11 +	.text
    3.12 +/* set_idt(uint32_t addr, uint16_t limit)
    3.13 + * loads the IDTR with the new address and limit for the IDT */
    3.14 +	.globl set_idt
    3.15 +set_idt:
    3.16 +	movl 4(%esp), %eax
    3.17 +	movl %eax, (addr)
    3.18 +	movw 8(%esp), %ax
    3.19 +	movw %ax, (lim)
    3.20 +	lidt (lim)
    3.21 +	ret
    3.22 +
    3.23 +/* interrupt entry with error code macro
    3.24 + * this macro generates an interrupt entry point for the
    3.25 + * exceptions which include error codes in the stack frame
    3.26 + */
    3.27 +	.macro ientry_err n name
    3.28 +	.globl intr_entry_\name
    3.29 +intr_entry_\name:
    3.30 +	pushl $\n
    3.31 +	jmp intr_entry_common
    3.32 +	.endm
    3.33 +
    3.34 +/* interrupt entry without error code macro
    3.35 + * this macro generates an interrupt entry point for the interrupts
    3.36 + * and exceptions which do not include error codes in the stack frame
    3.37 + * it pushes a dummy error code (0), to make the stack frame identical
    3.38 + */
    3.39 +	.macro ientry_noerr n name
    3.40 +	.globl intr_entry_\name
    3.41 +intr_entry_\name:
    3.42 +	pushl $0
    3.43 +	pushl $\n
    3.44 +	jmp intr_entry_common
    3.45 +	.endm
    3.46 +
    3.47 +/* common code used by all entry points. calls dispatch_intr()
    3.48 + * defined in intr.c
    3.49 + */
    3.50 +	.extern dispatch_intr
    3.51 +intr_entry_common:
    3.52 +	pusha
    3.53 +	call dispatch_intr
    3.54 +	popa
    3.55 +	/* remove error code and intr num from stack */
    3.56 +	add $8, %esp
    3.57 +	iret
    3.58 +
    3.59 +/* by including interrupts.h with ASM defined, the macros above
    3.60 + * are expanded to generate all required interrupt entry points
    3.61 + */
    3.62 +#define ASM
    3.63 +#include <interrupts.h>

     4.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     4.2 +++ b/src/intr.c	Sat Feb 19 04:41:51 2011 +0200
     4.3 @@ -0,0 +1,175 @@
     4.4 +#include <stdio.h>
     4.5 +#include "intr.h"
     4.6 +#include "desc.h"
     4.7 +#include "segm.h"
     4.8 +#include "asmops.h"
     4.9 +#include "panic.h"
    4.10 +
    4.11 +/* IDT gate descriptor bits */
    4.12 +#define GATE_TASK		(5 << 8)
    4.13 +#define GATE_INTR		(6 << 8)
    4.14 +#define GATE_TRAP		(7 << 8)
    4.15 +#define GATE_DEFAULT	(1 << 11)
    4.16 +#define GATE_PRESENT	(1 << 15)
    4.17 +
    4.18 +/* offset used to remap IRQ numbers (+32) */
    4.19 +#define IRQ_OFFSET		32
    4.20 +/* conversion macros between IRQ and interrupt numbers */
    4.21 +#define IRQ_TO_INTR(x)	((x) + IRQ_OFFSET)
    4.22 +#define INTR_TO_IRQ(x)	((x) - IRQ_OFFSET)
    4.23 +/* checks whether a particular interrupt is an remapped IRQ */
    4.24 +#define IS_IRQ(n)	((n) >= IRQ_OFFSET && (n) < IRQ_OFFSET + 16)
    4.25 +
    4.26 +/* PIC command and data ports */
    4.27 +#define PIC1_CMD	0x20
    4.28 +#define PIC1_DATA	0x21
    4.29 +#define PIC2_CMD	0xa0
    4.30 +#define PIC2_DATA	0xa1
    4.31 +
    4.32 +/* PIC initialization command word 1 bits */
    4.33 +#define ICW1_ICW4_NEEDED	(1 << 0)
    4.34 +#define ICW1_SINGLE			(1 << 1)
    4.35 +#define ICW1_INTERVAL4		(1 << 2)
    4.36 +#define ICW1_LEVEL			(1 << 3)
    4.37 +#define ICW1_INIT			(1 << 4)
    4.38 +/* PIC initialization command word 4 bits */
    4.39 +#define ICW4_8086			(1 << 0)
    4.40 +#define ICW4_AUTO_EOI		(1 << 1)
    4.41 +#define ICW4_BUF_SLAVE		(1 << 3) /* 1000 */
    4.42 +#define ICW4_BUF_MASTER		(3 << 2) /* 1100 */
    4.43 +#define ICW4_SPECIAL		(1 << 4)
    4.44 +
    4.45 +/* PIC operation command word 2 bits */
    4.46 +#define OCW2_EOI	(1 << 5)
    4.47 +
    4.48 +
    4.49 +/* structure used to pass the interrupt stack frame from the
    4.50 + * entry points to the C dispatch function.
    4.51 + */
    4.52 +struct intr_frame {
    4.53 +	/* registers pushed by pusha in intr_entry_* */
    4.54 +	uint32_t edi, esi, ebp, esp;
    4.55 +	uint32_t ebx, edx, ecx, eax;
    4.56 +	/* interrupt number and error code pushed in intr_entry_* */
    4.57 +	uint32_t inum, err;
    4.58 +	/* pushed by CPU during interrupt entry */
    4.59 +	uint32_t eip, cs, eflags;
    4.60 +};
    4.61 +
    4.62 +
    4.63 +static void init_pic(int offset);
    4.64 +static void gate_desc(desc_t *desc, uint16_t sel, uint32_t addr, int dpl, int type);
    4.65 +static void set_intr_entry(int num, void (*handler)(void));
    4.66 +static void end_of_irq(int irq);
    4.67 +
    4.68 +/* defined in intr-asm.S */
    4.69 +void set_idt(uint32_t addr, uint16_t limit);
    4.70 +void intr_entry_default(void);
    4.71 +
    4.72 +/* the IDT (interrupt descriptor table) */
    4.73 +static desc_t idt[256];
    4.74 +/* table of handler functions for all interrupts */
    4.75 +static intr_func_t intr_func[256];
    4.76 +
    4.77 +
    4.78 +void init_intr(void)
    4.79 +{
    4.80 +	int i;
    4.81 +
    4.82 +	set_idt((uint32_t)idt, sizeof idt - 1);
    4.83 +
    4.84 +	/* initialize all entry points and interrupt handlers */
    4.85 +	for(i=0; i<256; i++) {
    4.86 +		set_intr_entry(i, intr_entry_default);
    4.87 +		interrupt(i, 0);
    4.88 +	}
    4.89 +
    4.90 +	/* by including interrupts.h here (without ASM being defined)
    4.91 +	 * the series of INTR_ENTRY_* macros will be expanded to a series
    4.92 +	 * of function prototypes for all interrupt entry points and the
    4.93 +	 * corresponding calls to set_intr_entry to set up the IDT slots
    4.94 +	 */
    4.95 +#include "interrupts.h"
    4.96 +
    4.97 +	/* initialize the programmable interrupt controller
    4.98 +	 * setting up the maping of IRQs [0, 15] to interrupts [32, 47]
    4.99 +	 */
   4.100 +	init_pic(IRQ_OFFSET);
   4.101 +
   4.102 +	/* we're done setting up, enable interrupts before returning */
   4.103 +	enable_intr();
   4.104 +}
   4.105 +
   4.106 +/* set an interrupt handler function for a particular interrupt */
   4.107 +void interrupt(int intr_num, intr_func_t func)
   4.108 +{
   4.109 +	intr_func[intr_num] = func;
   4.110 +}
   4.111 +
   4.112 +/* this function is called from all interrupt entry points
   4.113 + * it calls the appropriate interrupt handlers if available and handles
   4.114 + * sending an end-of-interrupt command to the PICs when finished.
   4.115 + */
   4.116 +void dispatch_intr(struct intr_frame frm)
   4.117 +{
   4.118 +	if(intr_func[frm.inum]) {
   4.119 +		intr_func[frm.inum](frm.inum, frm.err);
   4.120 +	} else {
   4.121 +		if(frm.inum < 32) {
   4.122 +			panic("unhandled exception %d, error code: %d\n", frm.inum, frm.err);
   4.123 +		}
   4.124 +		printf("unhandled interrupt %d\n", frm.inum);
   4.125 +	}
   4.126 +
   4.127 +	if(IS_IRQ(frm.inum)) {
   4.128 +		end_of_irq(INTR_TO_IRQ(frm.inum));
   4.129 +	}
   4.130 +}
   4.131 +
   4.132 +static void init_pic(int offset)
   4.133 +{
   4.134 +	/* send ICW1 saying we'll follow with ICW4 later on */
   4.135 +	outb(ICW1_INIT | ICW1_ICW4_NEEDED, PIC1_CMD);
   4.136 +	outb(ICW1_INIT | ICW1_ICW4_NEEDED, PIC2_CMD);
   4.137 +	/* send ICW2 with IRQ remapping */
   4.138 +	outb(offset, PIC1_DATA);
   4.139 +	outb(offset + 8, PIC2_DATA);
   4.140 +	/* send ICW3 to setup the master/slave relationship */
   4.141 +	/* ... set bit3 = 3rd interrupt input has a slave */
   4.142 +	outb(4, PIC1_DATA);
   4.143 +	/* ... set slave ID to 2 */
   4.144 +	outb(2, PIC2_DATA);
   4.145 +	/* send ICW4 to set 8086 mode (no calls generated) */
   4.146 +	outb(ICW4_8086, PIC1_DATA);
   4.147 +	outb(ICW4_8086, PIC2_DATA);
   4.148 +	/* done, just reset the data port to 0 */
   4.149 +	outb(0, PIC1_DATA);
   4.150 +	outb(0, PIC2_DATA);
   4.151 +}
   4.152 +
   4.153 +static void gate_desc(desc_t *desc, uint16_t sel, uint32_t addr, int dpl, int type)
   4.154 +{
   4.155 +	/* first 16bit part is the low 16bits of the entry address */
   4.156 +	desc->d[0] = addr & 0xffff;
   4.157 +	/* second 16bit part is the segment selector for the entry code */
   4.158 +	desc->d[1] = sel;
   4.159 +	/* third 16bit part has the privilege level, type, and present bit */
   4.160 +	desc->d[2] = ((dpl & 3) << 13) | type | GATE_DEFAULT | GATE_PRESENT;
   4.161 +	/* last 16bit part is the high 16bits of the entry address */
   4.162 +	desc->d[3] = (addr & 0xffff0000) >> 16;
   4.163 +}
   4.164 +
   4.165 +#define IS_TRAP(n)	((n) < 20 && (n) != 2)
   4.166 +static void set_intr_entry(int num, void (*handler)(void))
   4.167 +{
   4.168 +	int type = IS_TRAP(num) ? GATE_TRAP : GATE_INTR;
   4.169 +	gate_desc(idt + num, selector(SEGM_KCODE, 0), (uint32_t)handler, 0, type);
   4.170 +}
   4.171 +
   4.172 +static void end_of_irq(int irq)
   4.173 +{
   4.174 +	if(irq > 7) {
   4.175 +		outb(OCW2_EOI, PIC2_CMD);
   4.176 +	}
   4.177 +	outb(OCW2_EOI, PIC1_CMD);
   4.178 +}

     5.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     5.2 +++ b/src/intr.h	Sat Feb 19 04:41:51 2011 +0200
     5.3 @@ -0,0 +1,13 @@
     5.4 +#ifndef INTR_H_
     5.5 +#define INTR_H_
     5.6 +
     5.7 +#include <inttypes.h>
     5.8 +
     5.9 +typedef void (*intr_func_t)(int, uint32_t);
    5.10 +
    5.11 +
    5.12 +void init_intr(void);
    5.13 +
    5.14 +void interrupt(int intr_num, intr_func_t func);
    5.15 +
    5.16 +#endif	/* INTR_H_ */

     6.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     6.2 +++ b/src/panic.c	Sat Feb 19 04:41:51 2011 +0200
     6.3 @@ -0,0 +1,16 @@
     6.4 +#include <stdio.h>
     6.5 +#include <stdarg.h>
     6.6 +#include "asmops.h"
     6.7 +
     6.8 +void panic(const char *fmt, ...)
     6.9 +{
    6.10 +	va_list ap;
    6.11 +
    6.12 +	printf("~~~~~ kernel panic ~~~~~\n");
    6.13 +	va_start(ap, fmt);
    6.14 +	vprintf(fmt, ap);
    6.15 +	va_end(ap);
    6.16 +
    6.17 +	disable_intr();
    6.18 +	halt_cpu();
    6.19 +}

     7.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     7.2 +++ b/src/panic.h	Sat Feb 19 04:41:51 2011 +0200
     7.3 @@ -0,0 +1,6 @@
     7.4 +#ifndef PANIC_H_
     7.5 +#define PANIC_H_
     7.6 +
     7.7 +void panic(const char *fmt, ...);
     7.8 +
     7.9 +#endif	/* PANIC_H_ */