kern
view src/intr.c @ 76:0fe6eef16335
holy fuck, copy_on_write didn't actually do the copy!!!!
| author | John Tsiombikas <nuclear@member.fsf.org> |
|---|---|
| date | Sat, 05 Nov 2011 04:53:46 +0200 |
| parents | fa65b4f45366 |
| children |
line source
1 #include <stdio.h>
2 #include "intr.h"
3 #include "desc.h"
4 #include "segm.h"
5 #include "asmops.h"
6 #include "panic.h"
7 #include "syscall.h"
9 /* IDT gate descriptor bits */
10 #define GATE_TASK (5 << 8)
11 #define GATE_INTR (6 << 8)
12 #define GATE_TRAP (7 << 8)
13 #define GATE_DEFAULT (1 << 11)
14 #define GATE_PRESENT (1 << 15)
16 /* PIC command and data ports */
17 #define PIC1_CMD 0x20
18 #define PIC1_DATA 0x21
19 #define PIC2_CMD 0xa0
20 #define PIC2_DATA 0xa1
22 /* PIC initialization command word 1 bits */
23 #define ICW1_ICW4_NEEDED (1 << 0)
24 #define ICW1_SINGLE (1 << 1)
25 #define ICW1_INTERVAL4 (1 << 2)
26 #define ICW1_LEVEL (1 << 3)
27 #define ICW1_INIT (1 << 4)
28 /* PIC initialization command word 4 bits */
29 #define ICW4_8086 (1 << 0)
30 #define ICW4_AUTO_EOI (1 << 1)
31 #define ICW4_BUF_SLAVE (1 << 3) /* 1000 */
32 #define ICW4_BUF_MASTER (3 << 2) /* 1100 */
33 #define ICW4_SPECIAL (1 << 4)
35 /* PIC operation command word 2 bits */
36 #define OCW2_EOI (1 << 5)
39 static void init_pic(int offset);
40 static void gate_desc(desc_t *desc, uint16_t sel, uint32_t addr, int dpl, int type);
41 static void set_intr_entry(int num, void (*handler)(void));
43 /* defined in intr-asm.S */
44 void set_idt(uint32_t addr, uint16_t limit);
45 void intr_entry_default(void);
47 /* the IDT (interrupt descriptor table) */
48 static desc_t idt[256];
49 /* table of handler functions for all interrupts */
50 static intr_func_t intr_func[256];
52 static struct intr_frame *cur_intr_frame;
53 static int eoi_pending;
56 void init_intr(void)
57 {
58 int i;
60 set_idt((uint32_t)idt, sizeof idt - 1);
62 /* initialize all entry points and interrupt handlers */
63 for(i=0; i<256; i++) {
64 set_intr_entry(i, intr_entry_default);
65 interrupt(i, 0);
66 }
68 /* by including interrupts.h here (without ASM being defined)
69 * the series of INTR_ENTRY_* macros will be expanded to a series
70 * of function prototypes for all interrupt entry points and the
71 * corresponding calls to set_intr_entry to set up the IDT slots
72 */
73 #include "interrupts.h"
75 /* initialize the programmable interrupt controller
76 * setting up the maping of IRQs [0, 15] to interrupts [32, 47]
77 */
78 init_pic(IRQ_OFFSET);
79 eoi_pending = 0;
80 }
82 /* retrieve the current interrupt frame.
83 * returns 0 when called during kernel init.
84 */
85 struct intr_frame *get_intr_frame(void)
86 {
87 return cur_intr_frame;
88 }
90 /* set an interrupt handler function for a particular interrupt */
91 void interrupt(int intr_num, intr_func_t func)
92 {
93 intr_func[intr_num] = func;
94 }
96 /* this function is called from all interrupt entry points
97 * it calls the appropriate interrupt handlers if available and handles
98 * sending an end-of-interrupt command to the PICs when finished.
99 */
100 void dispatch_intr(struct intr_frame frm)
101 {
102 cur_intr_frame = &frm;
104 if(IS_IRQ(frm.inum)) {
105 eoi_pending = frm.inum;
106 }
108 if(intr_func[frm.inum]) {
109 intr_func[frm.inum](frm.inum);
110 } else {
111 if(frm.inum < 32) {
112 panic("unhandled exception %d, error code: %d\n", frm.inum, frm.err);
113 }
114 printf("unhandled interrupt %d\n", frm.inum);
115 }
117 disable_intr();
118 if(eoi_pending) {
119 end_of_irq(INTR_TO_IRQ(eoi_pending));
120 }
121 }
123 static void init_pic(int offset)
124 {
125 /* send ICW1 saying we'll follow with ICW4 later on */
126 outb(ICW1_INIT | ICW1_ICW4_NEEDED, PIC1_CMD);
127 outb(ICW1_INIT | ICW1_ICW4_NEEDED, PIC2_CMD);
128 /* send ICW2 with IRQ remapping */
129 outb(offset, PIC1_DATA);
130 outb(offset + 8, PIC2_DATA);
131 /* send ICW3 to setup the master/slave relationship */
132 /* ... set bit3 = 3rd interrupt input has a slave */
133 outb(4, PIC1_DATA);
134 /* ... set slave ID to 2 */
135 outb(2, PIC2_DATA);
136 /* send ICW4 to set 8086 mode (no calls generated) */
137 outb(ICW4_8086, PIC1_DATA);
138 outb(ICW4_8086, PIC2_DATA);
139 /* done, just reset the data port to 0 */
140 outb(0, PIC1_DATA);
141 outb(0, PIC2_DATA);
142 }
144 static void gate_desc(desc_t *desc, uint16_t sel, uint32_t addr, int dpl, int type)
145 {
146 /* first 16bit part is the low 16bits of the entry address */
147 desc->d[0] = addr & 0xffff;
148 /* second 16bit part is the segment selector for the entry code */
149 desc->d[1] = sel;
150 /* third 16bit part has the privilege level, type, and present bit */
151 desc->d[2] = ((dpl & 3) << 13) | type | GATE_DEFAULT | GATE_PRESENT;
152 /* last 16bit part is the high 16bits of the entry address */
153 desc->d[3] = (addr & 0xffff0000) >> 16;
154 }
156 #define IS_TRAP(n) ((n) >= 32 && !IS_IRQ(n))
157 static void set_intr_entry(int num, void (*handler)(void))
158 {
159 int type = IS_TRAP(num) ? GATE_TRAP : GATE_INTR;
161 /* the syscall interrupt has to have a dpl of 3 otherwise calling it from
162 * user space will raise a general protection exception. All the rest should
163 * have a dpl of 0 to disallow user programs to execute critical interrupt
164 * handlers and possibly crashing the system.
165 */
166 int dpl = (num == SYSCALL_INT) ? 3 : 0;
168 gate_desc(idt + num, selector(SEGM_KCODE, 0), (uint32_t)handler, dpl, type);
169 }
171 void end_of_irq(int irq)
172 {
173 int intr_state = get_intr_state();
174 disable_intr();
176 if(!eoi_pending) {
177 return;
178 }
179 eoi_pending = 0;
181 if(irq > 7) {
182 outb(OCW2_EOI, PIC2_CMD);
183 }
184 outb(OCW2_EOI, PIC1_CMD);
186 set_intr_state(intr_state);
187 }