kern

annotate src/intr.c @ 27:7795225808b3

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moved enable_intr out of init_intr and after the kernel initialization is completed
author John Tsiombikas <nuclear@member.fsf.org>
date Sat, 09 Apr 2011 07:22:27 +0300
parents eaec918de072
children a2c6110bd24b 06172322fb76
rev   line source
nuclear@11 1 #include <stdio.h>
nuclear@11 2 #include "intr.h"
nuclear@11 3 #include "desc.h"
nuclear@11 4 #include "segm.h"
nuclear@11 5 #include "asmops.h"
nuclear@11 6 #include "panic.h"
nuclear@11 7
nuclear@11 8 /* IDT gate descriptor bits */
nuclear@11 9 #define GATE_TASK (5 << 8)
nuclear@11 10 #define GATE_INTR (6 << 8)
nuclear@11 11 #define GATE_TRAP (7 << 8)
nuclear@11 12 #define GATE_DEFAULT (1 << 11)
nuclear@11 13 #define GATE_PRESENT (1 << 15)
nuclear@11 14
nuclear@11 15 /* offset used to remap IRQ numbers (+32) */
nuclear@11 16 #define IRQ_OFFSET 32
nuclear@11 17 /* conversion macros between IRQ and interrupt numbers */
nuclear@11 18 #define IRQ_TO_INTR(x) ((x) + IRQ_OFFSET)
nuclear@11 19 #define INTR_TO_IRQ(x) ((x) - IRQ_OFFSET)
nuclear@11 20 /* checks whether a particular interrupt is an remapped IRQ */
nuclear@11 21 #define IS_IRQ(n) ((n) >= IRQ_OFFSET && (n) < IRQ_OFFSET + 16)
nuclear@11 22
nuclear@11 23 /* PIC command and data ports */
nuclear@11 24 #define PIC1_CMD 0x20
nuclear@11 25 #define PIC1_DATA 0x21
nuclear@11 26 #define PIC2_CMD 0xa0
nuclear@11 27 #define PIC2_DATA 0xa1
nuclear@11 28
nuclear@11 29 /* PIC initialization command word 1 bits */
nuclear@11 30 #define ICW1_ICW4_NEEDED (1 << 0)
nuclear@11 31 #define ICW1_SINGLE (1 << 1)
nuclear@11 32 #define ICW1_INTERVAL4 (1 << 2)
nuclear@11 33 #define ICW1_LEVEL (1 << 3)
nuclear@11 34 #define ICW1_INIT (1 << 4)
nuclear@11 35 /* PIC initialization command word 4 bits */
nuclear@11 36 #define ICW4_8086 (1 << 0)
nuclear@11 37 #define ICW4_AUTO_EOI (1 << 1)
nuclear@11 38 #define ICW4_BUF_SLAVE (1 << 3) /* 1000 */
nuclear@11 39 #define ICW4_BUF_MASTER (3 << 2) /* 1100 */
nuclear@11 40 #define ICW4_SPECIAL (1 << 4)
nuclear@11 41
nuclear@11 42 /* PIC operation command word 2 bits */
nuclear@11 43 #define OCW2_EOI (1 << 5)
nuclear@11 44
nuclear@11 45
nuclear@11 46 /* structure used to pass the interrupt stack frame from the
nuclear@11 47 * entry points to the C dispatch function.
nuclear@11 48 */
nuclear@11 49 struct intr_frame {
nuclear@11 50 /* registers pushed by pusha in intr_entry_* */
nuclear@11 51 uint32_t edi, esi, ebp, esp;
nuclear@11 52 uint32_t ebx, edx, ecx, eax;
nuclear@11 53 /* interrupt number and error code pushed in intr_entry_* */
nuclear@11 54 uint32_t inum, err;
nuclear@11 55 /* pushed by CPU during interrupt entry */
nuclear@11 56 uint32_t eip, cs, eflags;
nuclear@11 57 };
nuclear@11 58
nuclear@11 59
nuclear@11 60 static void init_pic(int offset);
nuclear@11 61 static void gate_desc(desc_t *desc, uint16_t sel, uint32_t addr, int dpl, int type);
nuclear@11 62 static void set_intr_entry(int num, void (*handler)(void));
nuclear@11 63 static void end_of_irq(int irq);
nuclear@11 64
nuclear@11 65 /* defined in intr-asm.S */
nuclear@11 66 void set_idt(uint32_t addr, uint16_t limit);
nuclear@11 67 void intr_entry_default(void);
nuclear@11 68
nuclear@11 69 /* the IDT (interrupt descriptor table) */
nuclear@11 70 static desc_t idt[256];
nuclear@11 71 /* table of handler functions for all interrupts */
nuclear@11 72 static intr_func_t intr_func[256];
nuclear@11 73
nuclear@11 74
nuclear@11 75 void init_intr(void)
nuclear@11 76 {
nuclear@11 77 int i;
nuclear@11 78
nuclear@11 79 set_idt((uint32_t)idt, sizeof idt - 1);
nuclear@11 80
nuclear@11 81 /* initialize all entry points and interrupt handlers */
nuclear@11 82 for(i=0; i<256; i++) {
nuclear@11 83 set_intr_entry(i, intr_entry_default);
nuclear@11 84 interrupt(i, 0);
nuclear@11 85 }
nuclear@11 86
nuclear@11 87 /* by including interrupts.h here (without ASM being defined)
nuclear@11 88 * the series of INTR_ENTRY_* macros will be expanded to a series
nuclear@11 89 * of function prototypes for all interrupt entry points and the
nuclear@11 90 * corresponding calls to set_intr_entry to set up the IDT slots
nuclear@11 91 */
nuclear@11 92 #include "interrupts.h"
nuclear@11 93
nuclear@11 94 /* initialize the programmable interrupt controller
nuclear@11 95 * setting up the maping of IRQs [0, 15] to interrupts [32, 47]
nuclear@11 96 */
nuclear@11 97 init_pic(IRQ_OFFSET);
nuclear@11 98 }
nuclear@11 99
nuclear@11 100 /* set an interrupt handler function for a particular interrupt */
nuclear@11 101 void interrupt(int intr_num, intr_func_t func)
nuclear@11 102 {
nuclear@11 103 intr_func[intr_num] = func;
nuclear@11 104 }
nuclear@11 105
nuclear@11 106 /* this function is called from all interrupt entry points
nuclear@11 107 * it calls the appropriate interrupt handlers if available and handles
nuclear@11 108 * sending an end-of-interrupt command to the PICs when finished.
nuclear@11 109 */
nuclear@11 110 void dispatch_intr(struct intr_frame frm)
nuclear@11 111 {
nuclear@11 112 if(intr_func[frm.inum]) {
nuclear@11 113 intr_func[frm.inum](frm.inum, frm.err);
nuclear@11 114 } else {
nuclear@11 115 if(frm.inum < 32) {
nuclear@11 116 panic("unhandled exception %d, error code: %d\n", frm.inum, frm.err);
nuclear@11 117 }
nuclear@11 118 printf("unhandled interrupt %d\n", frm.inum);
nuclear@11 119 }
nuclear@11 120
nuclear@11 121 if(IS_IRQ(frm.inum)) {
nuclear@11 122 end_of_irq(INTR_TO_IRQ(frm.inum));
nuclear@11 123 }
nuclear@11 124 }
nuclear@11 125
nuclear@11 126 static void init_pic(int offset)
nuclear@11 127 {
nuclear@11 128 /* send ICW1 saying we'll follow with ICW4 later on */
nuclear@11 129 outb(ICW1_INIT | ICW1_ICW4_NEEDED, PIC1_CMD);
nuclear@11 130 outb(ICW1_INIT | ICW1_ICW4_NEEDED, PIC2_CMD);
nuclear@11 131 /* send ICW2 with IRQ remapping */
nuclear@11 132 outb(offset, PIC1_DATA);
nuclear@11 133 outb(offset + 8, PIC2_DATA);
nuclear@11 134 /* send ICW3 to setup the master/slave relationship */
nuclear@11 135 /* ... set bit3 = 3rd interrupt input has a slave */
nuclear@11 136 outb(4, PIC1_DATA);
nuclear@11 137 /* ... set slave ID to 2 */
nuclear@11 138 outb(2, PIC2_DATA);
nuclear@11 139 /* send ICW4 to set 8086 mode (no calls generated) */
nuclear@11 140 outb(ICW4_8086, PIC1_DATA);
nuclear@11 141 outb(ICW4_8086, PIC2_DATA);
nuclear@11 142 /* done, just reset the data port to 0 */
nuclear@11 143 outb(0, PIC1_DATA);
nuclear@11 144 outb(0, PIC2_DATA);
nuclear@11 145 }
nuclear@11 146
nuclear@11 147 static void gate_desc(desc_t *desc, uint16_t sel, uint32_t addr, int dpl, int type)
nuclear@11 148 {
nuclear@11 149 /* first 16bit part is the low 16bits of the entry address */
nuclear@11 150 desc->d[0] = addr & 0xffff;
nuclear@11 151 /* second 16bit part is the segment selector for the entry code */
nuclear@11 152 desc->d[1] = sel;
nuclear@11 153 /* third 16bit part has the privilege level, type, and present bit */
nuclear@11 154 desc->d[2] = ((dpl & 3) << 13) | type | GATE_DEFAULT | GATE_PRESENT;
nuclear@11 155 /* last 16bit part is the high 16bits of the entry address */
nuclear@11 156 desc->d[3] = (addr & 0xffff0000) >> 16;
nuclear@11 157 }
nuclear@11 158
nuclear@12 159 #define IS_TRAP(n) ((n) < 32)
nuclear@11 160 static void set_intr_entry(int num, void (*handler)(void))
nuclear@11 161 {
nuclear@11 162 int type = IS_TRAP(num) ? GATE_TRAP : GATE_INTR;
nuclear@11 163 gate_desc(idt + num, selector(SEGM_KCODE, 0), (uint32_t)handler, 0, type);
nuclear@11 164 }
nuclear@11 165
nuclear@11 166 static void end_of_irq(int irq)
nuclear@11 167 {
nuclear@11 168 if(irq > 7) {
nuclear@11 169 outb(OCW2_EOI, PIC2_CMD);
nuclear@11 170 }
nuclear@11 171 outb(OCW2_EOI, PIC1_CMD);
nuclear@11 172 }