# HG changeset patch
# User John Tsiombikas <nuclear@member.fsf.org>
# Date 1547086607 -7200
# Node ID cacfa0888410a6c15c6a1e78e3c8addb5336698b

initial commit

diff -r 000000000000 -r cacfa0888410 .hgignore
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/.hgignore	Thu Jan 10 04:16:47 2019 +0200
@@ -0,0 +1,7 @@
+\.o$
+\.swp$
+^sin\.inc$
+\.gb$
+^test$
+\.tiles$
+\.tilemap$
diff -r 000000000000 -r cacfa0888410 Makefile
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/Makefile	Thu Jan 10 04:16:47 2019 +0200
@@ -0,0 +1,26 @@
+src = test.asm
+obj = test.o
+bin = test
+img = test.gb
+
+$(img): $(bin)
+	cp $< $@
+	rgbfix -v -p 0 $@
+
+$(bin): $(obj)
+	rgblink -o $@ $(obj)
+
+%.o: %.asm
+	rgbasm -o $@ $<
+
+test.o: test.asm sin.inc logo.tiles logo.tilemap
+
+.PHONY: clean
+clean:
+	rm -f $(obj) $(bin) $(img)
+
+logo.tiles: logo.png
+	rgbgfx -T -u -o $@ $<
+
+sin.inc:
+	./gensine >$@
diff -r 000000000000 -r cacfa0888410 gensine
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/gensine	Thu Jan 10 04:16:47 2019 +0200
@@ -0,0 +1,14 @@
+#!/usr/bin/python
+
+import math
+
+def main():
+    s = 16
+    x = 0.0
+    dx = 2.0 * math.pi / 256.0
+    for i in range(256):
+        sx = math.sin(x) * s# + s
+        print "\tdb ", int(sx)
+        x += dx
+
+main()
diff -r 000000000000 -r cacfa0888410 hw.inc
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hw.inc	Thu Jan 10 04:16:47 2019 +0200
@@ -0,0 +1,28 @@
+; vi:ft=rgbasm:
+REG_LCDC        equ $ff40
+REG_STAT        equ $ff41
+REG_SCY         equ $ff42
+REG_SCX         equ $ff43
+REG_LY          equ $ff44
+REG_LYC         equ $ff45
+REG_BGP         equ $ff47
+REG_OBP0        equ $ff48
+REG_OBP1        equ $ff49
+REG_WY          equ $ff4a
+REG_WX          equ $ff4b
+
+LCDC_BGON       equ $01
+LCDC_OBJON      equ $02
+LCDC_OBJ16      equ $04
+LCDC_BGMAP_9C00 equ $08
+LCDC_CHAR_8000  equ $10
+LCDC_WON        equ $20
+LCDC_WMAP_9C00  equ $40
+LCDC_DISPON     equ $80
+
+STAT_MODE_MASK	equ $03
+STAT_LYC	equ $04
+STAT_IE_HBLANK	equ $08
+STAT_IE_VBLANK	equ $10
+STAT_IE_OAM	equ $20
+STAT_IE_LYC	equ $40
diff -r 000000000000 -r cacfa0888410 logo.png
Binary file logo.png has changed
diff -r 000000000000 -r cacfa0888410 test.asm
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/test.asm	Thu Jan 10 04:16:47 2019 +0200
@@ -0,0 +1,144 @@
+; vi:ft=rgbasm:
+include "hw.inc"
+
+xoffs_center equ 4
+yoffs_center equ 12
+
+frame_ptr equ $ff80
+
+section "hdr", ROM0[$100]
+        nop
+        jp main
+
+rept $150 - $104
+        db 0
+endr
+
+section "text", ROM0
+
+main:
+	call init
+
+	xor a, a
+	ldh [frame_ptr], a
+.mainloop:
+	ldh a, [REG_LY]
+	cp a, 144
+	jr c, .wait_hsync
+
+	; we're in vsync, increment frame counter and wait for the next frame
+	ldh a, [frame_ptr]
+	inc a
+	ldh [frame_ptr], a
+.wait_newframe:
+	ldh a, [REG_LY]
+	cp a, 0
+	jr nz, .wait_newframe
+
+	; scanline code
+.wait_hsync:
+	ldh a, [REG_STAT]
+	and a, STAT_MODE_MASK
+	jr nz, .wait_hsync
+
+	ldh a, [frame_ptr]
+	ld d, a
+
+	xor a, a
+	ld b, a
+	ldh a, [REG_LY]
+	add a, d
+	ld c, a
+
+	ld hl, sintab
+	add hl, bc	; hl points to sin value (0-64)
+
+	ld a, yoffs_center
+	add a, [hl]
+	ldh [REG_SCY], a
+
+	; done, wait until we're out of hsync
+.wait_endhsync:
+	ldh a, [REG_STAT]
+	and a, STAT_MODE_MASK
+	jr z, .wait_endhsync
+
+	jr .mainloop 
+
+
+	di
+.end:   halt
+        nop
+        jp .end
+
+init:
+	call wait_vsync
+	xor a, a
+	ldh [REG_LCDC], a
+
+	; setup identity palette
+	ld a, $1b
+	ldh [REG_BGP], a
+
+
+	; copy tiles
+	ld hl, $8000
+	ld de, tiles
+	ld bc, tiles_end - tiles
+.copytiles:
+	ld a, [de]
+	ld [hl+], a
+	inc de
+	dec bc
+	ld a, b
+	or c
+	jp nz, .copytiles
+
+	; copy tilemap
+	ld hl, $9800
+	ld de, tilemap
+	ld b, 21
+.copymap:
+	ld c, 21
+.copymaprow:
+	ld a, [de]
+	inc de
+	ld [hl+], a
+	dec c
+	jr nz, .copymaprow
+
+	push bc
+	ld bc, 11
+	add hl, bc
+	pop bc
+
+	dec b
+	jr nz, .copymap
+
+	; center viewport
+	ld a, yoffs_center
+	ldh [REG_SCY], a
+	ld a, xoffs_center
+	ldh [REG_SCX], a
+
+	; configure LCD
+	ld a, LCDC_DISPON | LCDC_CHAR_8000 | LCDC_BGON
+	ldh [REG_LCDC], a
+	ret
+
+wait_vsync:
+	ldh a, [REG_LY]
+	cp a, 144
+	jr c, wait_vsync
+	ret
+
+section "data", ROM0, align[8]
+sintab:
+include "sin.inc"
+
+tiles:
+incbin "logo.tiles"
+tiles_end:
+tilemap:
+incbin "logo.tilemap"
+tilemap_end: