gb_test2

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initial commit
author John Tsiombikas <nuclear@member.fsf.org>
date Thu, 10 Jan 2019 04:16:47 +0200
parents
children d63782badb6b
line source
1 ; vi:ft=rgbasm:
2 include "hw.inc"
3
4 xoffs_center equ 4
5 yoffs_center equ 12
6
7 frame_ptr equ $ff80
8
9 section "hdr", ROM0[$100]
10 nop
11 jp main
12
13 rept $150 - $104
14 db 0
15 endr
16
17 section "text", ROM0
18
19 main:
20 call init
21
22 xor a, a
23 ldh [frame_ptr], a
24 .mainloop:
25 ldh a, [REG_LY]
26 cp a, 144
27 jr c, .wait_hsync
28
29 ; we're in vsync, increment frame counter and wait for the next frame
30 ldh a, [frame_ptr]
31 inc a
32 ldh [frame_ptr], a
33 .wait_newframe:
34 ldh a, [REG_LY]
35 cp a, 0
36 jr nz, .wait_newframe
37
38 ; scanline code
39 .wait_hsync:
40 ldh a, [REG_STAT]
41 and a, STAT_MODE_MASK
42 jr nz, .wait_hsync
43
44 ldh a, [frame_ptr]
45 ld d, a
46
47 xor a, a
48 ld b, a
49 ldh a, [REG_LY]
50 add a, d
51 ld c, a
52
53 ld hl, sintab
54 add hl, bc ; hl points to sin value (0-64)
55
56 ld a, yoffs_center
57 add a, [hl]
58 ldh [REG_SCY], a
59
60 ; done, wait until we're out of hsync
61 .wait_endhsync:
62 ldh a, [REG_STAT]
63 and a, STAT_MODE_MASK
64 jr z, .wait_endhsync
65
66 jr .mainloop
67
68
69 di
70 .end: halt
71 nop
72 jp .end
73
74 init:
75 call wait_vsync
76 xor a, a
77 ldh [REG_LCDC], a
78
79 ; setup identity palette
80 ld a, $1b
81 ldh [REG_BGP], a
82
83
84 ; copy tiles
85 ld hl, $8000
86 ld de, tiles
87 ld bc, tiles_end - tiles
88 .copytiles:
89 ld a, [de]
90 ld [hl+], a
91 inc de
92 dec bc
93 ld a, b
94 or c
95 jp nz, .copytiles
96
97 ; copy tilemap
98 ld hl, $9800
99 ld de, tilemap
100 ld b, 21
101 .copymap:
102 ld c, 21
103 .copymaprow:
104 ld a, [de]
105 inc de
106 ld [hl+], a
107 dec c
108 jr nz, .copymaprow
109
110 push bc
111 ld bc, 11
112 add hl, bc
113 pop bc
114
115 dec b
116 jr nz, .copymap
117
118 ; center viewport
119 ld a, yoffs_center
120 ldh [REG_SCY], a
121 ld a, xoffs_center
122 ldh [REG_SCX], a
123
124 ; configure LCD
125 ld a, LCDC_DISPON | LCDC_CHAR_8000 | LCDC_BGON
126 ldh [REG_LCDC], a
127 ret
128
129 wait_vsync:
130 ldh a, [REG_LY]
131 cp a, 144
132 jr c, wait_vsync
133 ret
134
135 section "data", ROM0, align[8]
136 sintab:
137 include "sin.inc"
138
139 tiles:
140 incbin "logo.tiles"
141 tiles_end:
142 tilemap:
143 incbin "logo.tilemap"
144 tilemap_end: