1.1 --- a/test.asm	Thu Jan 10 04:16:47 2019 +0200
     1.2 +++ b/test.asm	Thu Jan 10 04:47:42 2019 +0200
     1.3 @@ -46,17 +46,52 @@
     1.4  
     1.5  	xor a, a
     1.6  	ld b, a
     1.7 +
     1.8  	ldh a, [REG_LY]
     1.9 -	add a, d
    1.10 +	add a, d	; add frame number
    1.11  	ld c, a
    1.12  
    1.13  	ld hl, sintab
    1.14 -	add hl, bc	; hl points to sin value (0-64)
    1.15 +	add hl, bc	; hl now points to the sine value
    1.16  
    1.17 -	ld a, yoffs_center
    1.18 -	add a, [hl]
    1.19 +	ld a, [hl]
    1.20 +
    1.21 +	; add a half-octave sine
    1.22 +	ld e, a		; save first sine to e
    1.23 +	sla d
    1.24 +	ld a, [REG_LY]
    1.25 +	sla a
    1.26 +	add a, d
    1.27 +	ld c, a
    1.28 +	srl d
    1.29 +
    1.30 +	ld hl, sintab
    1.31 +	add hl, bc
    1.32 +	ld a, [hl]
    1.33 +	sra a
    1.34 +	add a, e	; add previously saved sine
    1.35 +
    1.36 +	add a, yoffs_center
    1.37  	ldh [REG_SCY], a
    1.38  
    1.39 +	; do something for SCX too
    1.40 +	ld a, d
    1.41 +	sla a
    1.42 +	ld d, a
    1.43 +
    1.44 +	ldh a, [REG_LY]
    1.45 +	add a, 32
    1.46 +	add a, d	; add frame number
    1.47 +	ld c, a
    1.48 +
    1.49 +	ld hl, sintab
    1.50 +	add hl, bc
    1.51 +
    1.52 +	ld a, [hl]
    1.53 +	sra a
    1.54 +	add a, xoffs_center
    1.55 +	ldh [REG_SCX], a
    1.56 +
    1.57  	; done, wait until we're out of hsync
    1.58  .wait_endhsync:
    1.59  	ldh a, [REG_STAT]