gb_test2

diff test.asm @ 0:cacfa0888410

initial commit
author John Tsiombikas <nuclear@member.fsf.org>
date Thu, 10 Jan 2019 04:16:47 +0200
parents
children d63782badb6b
line diff
     1.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.2 +++ b/test.asm	Thu Jan 10 04:16:47 2019 +0200
     1.3 @@ -0,0 +1,144 @@
     1.4 +; vi:ft=rgbasm:
     1.5 +include "hw.inc"
     1.6 +
     1.7 +xoffs_center equ 4
     1.8 +yoffs_center equ 12
     1.9 +
    1.10 +frame_ptr equ $ff80
    1.11 +
    1.12 +section "hdr", ROM0[$100]
    1.13 +        nop
    1.14 +        jp main
    1.15 +
    1.16 +rept $150 - $104
    1.17 +        db 0
    1.18 +endr
    1.19 +
    1.20 +section "text", ROM0
    1.21 +
    1.22 +main:
    1.23 +	call init
    1.24 +
    1.25 +	xor a, a
    1.26 +	ldh [frame_ptr], a
    1.27 +.mainloop:
    1.28 +	ldh a, [REG_LY]
    1.29 +	cp a, 144
    1.30 +	jr c, .wait_hsync
    1.31 +
    1.32 +	; we're in vsync, increment frame counter and wait for the next frame
    1.33 +	ldh a, [frame_ptr]
    1.34 +	inc a
    1.35 +	ldh [frame_ptr], a
    1.36 +.wait_newframe:
    1.37 +	ldh a, [REG_LY]
    1.38 +	cp a, 0
    1.39 +	jr nz, .wait_newframe
    1.40 +
    1.41 +	; scanline code
    1.42 +.wait_hsync:
    1.43 +	ldh a, [REG_STAT]
    1.44 +	and a, STAT_MODE_MASK
    1.45 +	jr nz, .wait_hsync
    1.46 +
    1.47 +	ldh a, [frame_ptr]
    1.48 +	ld d, a
    1.49 +
    1.50 +	xor a, a
    1.51 +	ld b, a
    1.52 +	ldh a, [REG_LY]
    1.53 +	add a, d
    1.54 +	ld c, a
    1.55 +
    1.56 +	ld hl, sintab
    1.57 +	add hl, bc	; hl points to sin value (0-64)
    1.58 +
    1.59 +	ld a, yoffs_center
    1.60 +	add a, [hl]
    1.61 +	ldh [REG_SCY], a
    1.62 +
    1.63 +	; done, wait until we're out of hsync
    1.64 +.wait_endhsync:
    1.65 +	ldh a, [REG_STAT]
    1.66 +	and a, STAT_MODE_MASK
    1.67 +	jr z, .wait_endhsync
    1.68 +
    1.69 +	jr .mainloop 
    1.70 +
    1.71 +
    1.72 +	di
    1.73 +.end:   halt
    1.74 +        nop
    1.75 +        jp .end
    1.76 +
    1.77 +init:
    1.78 +	call wait_vsync
    1.79 +	xor a, a
    1.80 +	ldh [REG_LCDC], a
    1.81 +
    1.82 +	; setup identity palette
    1.83 +	ld a, $1b
    1.84 +	ldh [REG_BGP], a
    1.85 +
    1.86 +
    1.87 +	; copy tiles
    1.88 +	ld hl, $8000
    1.89 +	ld de, tiles
    1.90 +	ld bc, tiles_end - tiles
    1.91 +.copytiles:
    1.92 +	ld a, [de]
    1.93 +	ld [hl+], a
    1.94 +	inc de
    1.95 +	dec bc
    1.96 +	ld a, b
    1.97 +	or c
    1.98 +	jp nz, .copytiles
    1.99 +
   1.100 +	; copy tilemap
   1.101 +	ld hl, $9800
   1.102 +	ld de, tilemap
   1.103 +	ld b, 21
   1.104 +.copymap:
   1.105 +	ld c, 21
   1.106 +.copymaprow:
   1.107 +	ld a, [de]
   1.108 +	inc de
   1.109 +	ld [hl+], a
   1.110 +	dec c
   1.111 +	jr nz, .copymaprow
   1.112 +
   1.113 +	push bc
   1.114 +	ld bc, 11
   1.115 +	add hl, bc
   1.116 +	pop bc
   1.117 +
   1.118 +	dec b
   1.119 +	jr nz, .copymap
   1.120 +
   1.121 +	; center viewport
   1.122 +	ld a, yoffs_center
   1.123 +	ldh [REG_SCY], a
   1.124 +	ld a, xoffs_center
   1.125 +	ldh [REG_SCX], a
   1.126 +
   1.127 +	; configure LCD
   1.128 +	ld a, LCDC_DISPON | LCDC_CHAR_8000 | LCDC_BGON
   1.129 +	ldh [REG_LCDC], a
   1.130 +	ret
   1.131 +
   1.132 +wait_vsync:
   1.133 +	ldh a, [REG_LY]
   1.134 +	cp a, 144
   1.135 +	jr c, wait_vsync
   1.136 +	ret
   1.137 +
   1.138 +section "data", ROM0, align[8]
   1.139 +sintab:
   1.140 +include "sin.inc"
   1.141 +
   1.142 +tiles:
   1.143 +incbin "logo.tiles"
   1.144 +tiles_end:
   1.145 +tilemap:
   1.146 +incbin "logo.tilemap"
   1.147 +tilemap_end: