# HG changeset patch
# User John Tsiombikas <nuclear@member.fsf.org>
# Date 1489360257 -7200
# Node ID f14e14abe14c8bd356e43524d879266b92a8578f
# Parent  ff8af8351282a4010fbc96a579f6f49d1cc1db0c
delays?

diff -r ff8af8351282 -r f14e14abe14c main.c
--- a/main.c	Sun Mar 12 23:43:41 2017 +0200
+++ b/main.c	Mon Mar 13 01:10:57 2017 +0200
@@ -190,9 +190,11 @@
 
 	/* no need for DDRB change, we drive the bus by default in programming mode */
 	PORTB = val;	/* set data */
+	_delay_us(0.1);
 
 	/* pulse WE */
 	PORTD &= ~WE_BIT;
+	_delay_us(0.1);
 	/* WE should be low for at least 9ns, which is way faster than we can toggle it anyway */
 	PORTD |= WE_BIT;
 }
@@ -207,7 +209,7 @@
 
 	DDRB = 0;			/* release the data bus */
 	PORTD &= ~OE_BIT;	/* assert OE (output enable) */
-	_delay_us(0.1);
+	_delay_us(1);
 	val = PINB;			/* read the data */
 	PORTD |= OE_BIT;	/* deassert OE */
 	DDRB = 0xff;		/* take back the bus */