amiga_boottest
view src/hwregs.h @ 4:995d42b33974
serial output
| author | John Tsiombikas <nuclear@member.fsf.org> |
|---|---|
| date | Fri, 23 Feb 2018 13:29:37 +0200 |
| parents | 48093e4bd99a |
| children |
line source
1 #ifndef HWREGS_H_
2 #define HWREGS_H_
4 #include "inttypes.h"
6 #define REG_BASE_ADDR 0xdff000
8 #define REGN_BLTDDAT 0x000
9 #define REGN_DMACONR 0x002
10 #define REGN_VPOSR 0x004
11 #define REGN_VHPOSR 0x006
12 #define REGN_DSKDATR 0x008
13 #define REGN_JOY0DAT 0x00a
14 #define REGN_JOY1DAT 0x00c
15 #define REGN_CLXDAT 0x00e
16 #define REGN_ADKCONR 0x010
17 #define REGN_POT0DAT 0x012
18 #define REGN_POT1DAT 0x014
19 #define REGN_POTGOR 0x016
20 #define REGN_SERDATR 0x018
21 #define REGN_DSKBYTR 0x01a
22 #define REGN_INTENAR 0x01c
23 #define REGN_INTREQR 0x01e
24 #define REGN_DSKPTH 0x020
25 #define REGN_DSKPTL 0x022
26 #define REGN_DSKLEN 0x024
27 #define REGN_DSKDAT 0x026
28 #define REGN_REFPTR 0x028
29 #define REGN_VPOSW 0x02a
30 #define REGN_VHPOSW 0x02c
31 #define REGN_COPCON 0x02e
32 #define REGN_SERDAT 0x030
33 #define REGN_SERPER 0x032
34 #define REGN_POTGO 0x034
35 #define REGN_JOYTEST 0x036
36 #define REGN_STREQU 0x038
37 #define REGN_STRVBL 0x03a
38 #define REGN_STRHOR 0x03c
39 #define REGN_STRLONG 0x03e
40 #define REGN_BLTCON0 0x040
41 #define REGN_BLTCON1 0x042
42 #define REGN_BLTAFWM 0x044
43 #define REGN_BLTALWM 0x046
44 #define REGN_BLTCPTH 0x048
45 #define REGN_BLTCPTL 0x04a
46 #define REGN_BLTBPTH 0x04c
47 #define REGN_BLTBPTL 0x04e
48 #define REGN_BLTAPTH 0x050
49 #define REGN_BLTAPTL 0x052
50 #define REGN_BLTDPTH 0x054
51 #define REGN_BLTDPTL 0x056
52 #define REGN_BLTSIZE 0x058
53 #define REGN_BLTCON0L 0x05a
54 #define REGN_BLTSIZV 0x05c
55 #define REGN_BLTSIZH 0x05e
56 #define REGN_BLTCMOD 0x060
57 #define REGN_BLTBMOD 0x062
58 #define REGN_BLTAMOD 0x064
59 #define REGN_BLTDMOD 0x066
60 #define REGN_BLTCDAT 0x070
61 #define REGN_BLTBDAT 0x072
62 #define REGN_BLTADAT 0x074
63 #define REGN_SPRHDAT 0x078
64 #define REGN_DENISEID 0x07c
65 #define REGN_DSKSYNC 0x07e
66 #define REGN_COP1LCH 0x080
67 #define REGN_COP1LCL 0x082
68 #define REGN_COP2LCH 0x084
69 #define REGN_COP2LCL 0x086
70 #define REGN_CMPJMP1 0x088
71 #define REGN_CMPJMP2 0x08a
72 #define REGN_COPINS 0x08c
73 #define REGN_DIWSTART 0x08e
74 #define REGN_DIWSTOP 0x090
75 #define REGN_DDFSTART 0x092
76 #define REGN_DDFSTOP 0x094
77 #define REGN_DMACON 0x096
78 #define REGN_CLXCON 0x098
79 #define REGN_INTENA 0x09a
80 #define REGN_INTREQ 0x09c
81 #define REGN_ADKCON 0x09e
83 #define REGN_AUDIO_LCH(c) (REGN_AUDIO0_BASE + (c) * 16 + 0)
84 #define REGN_AUDIO_LCL(c) (REGN_AUDIO0_BASE + (c) * 16 + 2)
85 #define REGN_AUDIO_LEN(c) (REGN_AUDIO0_BASE + (c) * 16 + 4)
86 #define REGN_AUDIO_PER(c) (REGN_AUDIO0_BASE + (c) * 16 + 6)
87 #define REGN_AUDIO_VOL(c) (REGN_AUDIO0_BASE + (c) * 16 + 8)
88 #define REGN_AUDIO_DAT(c) (REGN_AUDIO0_BASE + (c) * 16 + 10)
90 #define REGN_AUDIO0_BASE 0x0a0
91 #define REGN_AUD0LCH (REGN_AUDIO0_BASE + 0)
92 #define REGN_AUD0LCL (REGN_AUDIO0_BASE + 2)
93 #define REGN_AUD0LEN (REGN_AUDIO0_BASE + 4)
94 #define REGN_AUD0PER (REGN_AUDIO0_BASE + 6)
95 #define REGN_AUD0VOL (REGN_AUDIO0_BASE + 8)
96 #define REGN_AUD0DAT (REGN_AUDIO0_BASE + 10)
97 #define REGN_AUDIO1_BASE 0x0b0
98 #define REGN_AUD1LCH (REGN_AUDIO1_BASE + 0)
99 #define REGN_AUD1LCL (REGN_AUDIO1_BASE + 2)
100 #define REGN_AUD1LEN (REGN_AUDIO1_BASE + 4)
101 #define REGN_AUD1PER (REGN_AUDIO1_BASE + 6)
102 #define REGN_AUD1VOL (REGN_AUDIO1_BASE + 8)
103 #define REGN_AUD1DAT (REGN_AUDIO1_BASE + 10)
104 #define REGN_AUDIO2_BASE 0x0c0
105 #define REGN_AUD2LCH (REGN_AUDIO2_BASE + 0)
106 #define REGN_AUD2LCL (REGN_AUDIO2_BASE + 2)
107 #define REGN_AUD2LEN (REGN_AUDIO2_BASE + 4)
108 #define REGN_AUD2PER (REGN_AUDIO2_BASE + 6)
109 #define REGN_AUD2VOL (REGN_AUDIO2_BASE + 8)
110 #define REGN_AUD2DAT (REGN_AUDIO2_BASE + 10)
111 #define REGN_AUDIO3_BASE 0x0d0
112 #define REGN_AUD3LCH (REGN_AUDIO3_BASE + 0)
113 #define REGN_AUD3LCL (REGN_AUDIO3_BASE + 2)
114 #define REGN_AUD3LEN (REGN_AUDIO3_BASE + 4)
115 #define REGN_AUD3PER (REGN_AUDIO3_BASE + 6)
116 #define REGN_AUD3VOL (REGN_AUDIO3_BASE + 8)
117 #define REGN_AUD3DAT (REGN_AUDIO3_BASE + 10)
119 #define REGN_BPL1PTH 0x0e0
120 #define REGN_BPL1PTL 0x0e2
121 #define REGN_BPL2PTH 0x0e4
122 #define REGN_BPL2PTL 0x0e6
123 #define REGN_BPL3PTH 0x0e8
124 #define REGN_BPL3PTL 0x0ea
125 #define REGN_BPL4PTH 0x0ec
126 #define REGN_BPL4PTL 0x0ee
127 #define REGN_BPL5PTH 0x0f0
128 #define REGN_BPL5PTL 0x0f2
129 #define REGN_BPL6PTH 0x0f4
130 #define REGN_BPL6PTL 0x0f6
131 #define REGN_BPLCON0 0x100
132 #define REGN_BPLCON1 0x102
133 #define REGN_BPLCON2 0x104
134 #define REGN_BPLCON3 0x106
135 #define REGN_BPL1MOD 0x108
136 #define REGN_BPL2MOD 0x10a
137 #define REGN_BPL1DAT 0x110
138 #define REGN_BPL2DAT 0x112
139 #define REGN_BPL3DAT 0x114
140 #define REGN_BPL4DAT 0x116
141 #define REGN_BPL5DAT 0x118
142 #define REGN_BPL6DAT 0x11a
144 #define REGN_SPR0PTH 0x120
145 #define REGN_SPR0PTL 0x122
146 #define REGN_SPR1PTH 0x124
147 #define REGN_SPR1PTL 0x126
148 #define REGN_SPR2PTH 0x128
149 #define REGN_SPR2PTL 0x12a
150 #define REGN_SPR3PTH 0x12c
151 #define REGN_SPR3PTL 0x12e
152 #define REGN_SPR4PTH 0x130
153 #define REGN_SPR4PTL 0x132
154 #define REGN_SPR5PTH 0x134
155 #define REGN_SPR5PTL 0x136
156 #define REGN_SPR6PTH 0x138
157 #define REGN_SPR6PTL 0x13a
158 #define REGN_SPR7PTH 0x13c
159 #define REGN_SPR7PTL 0x13e
161 #define REGN_SPRITE_POS(s) (REGN_SPRITE0_BASE + (s) * 8 + 0)
162 #define REGN_SPRITE_CTL(s) (REGN_SPRITE0_BASE + (s) * 8 + 2)
163 #define REGN_SPRITE_DATA(s) (REGN_SPRITE0_BASE + (s) * 8 + 4)
164 #define REGN_SPRITE_DATB(s) (REGN_SPRITE0_BASE + (s) * 8 + 6)
166 #define REGN_SPRITE0_BASE 0x140
167 #define REGN_SPR0POS REGN_SPRITE_POS(0)
168 #define REGN_SPR0CTL REGN_SPRITE_CTL(0)
169 #define REGN_SPR0DATA REGN_SPRITE_DATA(0)
170 #define REGN_SPR0DATB REGN_SPRITE_DATB(0)
171 #define REGN_SPRITE1_BASE 0x148
172 #define REGN_SPR1POS REGN_SPRITE_POS(1)
173 #define REGN_SPR1CTL REGN_SPRITE_CTL(1)
174 #define REGN_SPR1DATA REGN_SPRITE_DATA(1)
175 #define REGN_SPR1DATB REGN_SPRITE_DATB(1)
176 #define REGN_SPRITE2_BASE 0x150
177 #define REGN_SPR2POS REGN_SPRITE_POS(2)
178 #define REGN_SPR2CTL REGN_SPRITE_CTL(2)
179 #define REGN_SPR2DATA REGN_SPRITE_DATA(2)
180 #define REGN_SPR2DATB REGN_SPRITE_DATB(2)
181 #define REGN_SPRITE3_BASE 0x158
182 #define REGN_SPR3POS REGN_SPRITE_POS(3)
183 #define REGN_SPR3CTL REGN_SPRITE_CTL(3)
184 #define REGN_SPR3DATA REGN_SPRITE_DATA(3)
185 #define REGN_SPR3DATB REGN_SPRITE_DATB(3)
186 #define REGN_SPRITE4_BASE 0x160
187 #define REGN_SPR4POS REGN_SPRITE_POS(4)
188 #define REGN_SPR4CTL REGN_SPRITE_CTL(4)
189 #define REGN_SPR4DATA REGN_SPRITE_DATA(4)
190 #define REGN_SPR4DATB REGN_SPRITE_DATB(4)
191 #define REGN_SPRITE5_BASE 0x168
192 #define REGN_SPR5POS REGN_SPRITE_POS(5)
193 #define REGN_SPR5CTL REGN_SPRITE_CTL(5)
194 #define REGN_SPR5DATA REGN_SPRITE_DATA(5)
195 #define REGN_SPR5DATB REGN_SPRITE_DATB(5)
196 #define REGN_SPRITE6_BASE 0x170
197 #define REGN_SPR6POS REGN_SPRITE_POS(6)
198 #define REGN_SPR6CTL REGN_SPRITE_CTL(6)
199 #define REGN_SPR6DATA REGN_SPRITE_DATA(6)
200 #define REGN_SPR6DATB REGN_SPRITE_DATB(6)
201 #define REGN_SPRITE7_BASE 0x178
202 #define REGN_SPR7POS REGN_SPRITE_POS(7)
203 #define REGN_SPR7CTL REGN_SPRITE_CTL(7)
204 #define REGN_SPR7DATA REGN_SPRITE_DATA(7)
205 #define REGN_SPR7DATB REGN_SPRITE_DATB(7)
207 #define REGN_COLOR_BASE 0x180
208 #define REGN_COLOR(idx) (REGN_COLOR_BASE + (idx) * 2)
210 #define REGN_COLOR0 REGN_COLOR(0)
211 #define REGN_COLOR1 REGN_COLOR(1)
212 #define REGN_COLOR2 REGN_COLOR(2)
213 #define REGN_COLOR3 REGN_COLOR(3)
214 #define REGN_COLOR4 REGN_COLOR(4)
215 #define REGN_COLOR5 REGN_COLOR(5)
216 #define REGN_COLOR6 REGN_COLOR(6)
217 #define REGN_COLOR7 REGN_COLOR(7)
218 #define REGN_COLOR8 REGN_COLOR(8)
219 #define REGN_COLOR9 REGN_COLOR(9)
220 #define REGN_COLOR10 REGN_COLOR(10)
221 #define REGN_COLOR11 REGN_COLOR(11)
222 #define REGN_COLOR12 REGN_COLOR(12)
223 #define REGN_COLOR13 REGN_COLOR(13)
224 #define REGN_COLOR14 REGN_COLOR(14)
225 #define REGN_COLOR15 REGN_COLOR(15)
226 #define REGN_COLOR16 REGN_COLOR(16)
227 #define REGN_COLOR17 REGN_COLOR(17)
228 #define REGN_COLOR18 REGN_COLOR(18)
229 #define REGN_COLOR19 REGN_COLOR(19)
230 #define REGN_COLOR20 REGN_COLOR(20)
231 #define REGN_COLOR21 REGN_COLOR(21)
232 #define REGN_COLOR22 REGN_COLOR(22)
233 #define REGN_COLOR23 REGN_COLOR(23)
234 #define REGN_COLOR24 REGN_COLOR(24)
235 #define REGN_COLOR25 REGN_COLOR(25)
236 #define REGN_COLOR26 REGN_COLOR(26)
237 #define REGN_COLOR27 REGN_COLOR(27)
238 #define REGN_COLOR28 REGN_COLOR(28)
239 #define REGN_COLOR29 REGN_COLOR(29)
240 #define REGN_COLOR30 REGN_COLOR(30)
241 #define REGN_COLOR31 REGN_COLOR(31)
243 #define REGN_HTOTAL 0x1c0
244 #define REGN_HSSTOP 0x1c2
245 #define REGN_HBSTART 0x1c4
246 #define REGN_HBSTOP 0x1c6
247 #define REGN_VTOTAL 0x1c8
248 #define REGN_VSSTOP 0x1ca
249 #define REGN_VBSTART 0x1cc
250 #define REGN_VBSTOP 0x1ce
251 #define REGN_BEAMCON0 0x1dc
252 #define REGN_HSSTART 0x1de
253 #define REGN_VSSTART 0x1e0
254 #define REGN_HCENTER 0x1e2
255 #define REGN_DIWHIGH 0x1e4
257 #define REGN_COP1LCH 0x080
258 #define REGN_COP1LCL 0x082
259 #define REGN_COP2LCH 0x084
260 #define REGN_COP2LCL 0x086
261 #define REGN_COPJMP1 0x088
262 #define REGN_COPJMP2 0x08a
264 #define REG(r) (*(volatile uint16_t*)(REG_BASE_ADDR | (r)))
266 #define REG_CIAA_PORTA *(volatile uint8_t*)0xbfe001
268 #define REG_INTENA REG(REGN_INTENA)
269 #define REG_INTENAR REG(REGN_INTENAR)
270 #define REG_INTREQ REG(REGN_INTREQ)
271 #define REG_INTREQR REG(REGN_INTREQR)
272 #define REG_ADKCON REG(REGN_ADKCON)
273 #define REG_ADKCONR REG(REGN_ADKCONR)
274 #define REG_DMACON REG(REGN_DMACON)
275 #define REG_DMACONR REG(REGN_DMACONR)
276 #define REG_BPLCON0 REG(REGN_BPLCON0)
277 #define REG_BPLCON1 REG(REGN_BPLCON1)
278 #define REG_BPLCON2 REG(REGN_BPLCON2)
279 #define REG_BPL1PTH REG(REGN_BPL1PTH)
280 #define REG_BPL2PTH REG(REGN_BPL2PTH)
281 #define REG_BPL3PTH REG(REGN_BPL3PTH)
282 #define REG_BPL4PTH REG(REGN_BPL4PTH)
283 #define REG_BPL5PTH REG(REGN_BPL5PTH)
284 #define REG_BPL6PTH REG(REGN_BPL6PTH)
285 #define REG_BPL1PTL REG(REGN_BPL1PTL)
286 #define REG_BPL2PTL REG(REGN_BPL2PTL)
287 #define REG_BPL3PTL REG(REGN_BPL3PTL)
288 #define REG_BPL4PTL REG(REGN_BPL4PTL)
289 #define REG_BPL5PTL REG(REGN_BPL5PTL)
290 #define REG_BPL6PTL REG(REGN_BPL6PTL)
291 #define REG32_BPL1PT *(volatile uint32_t*)(REG_BASE_ADDR | REGN_BPL1PTH)
292 #define REG32_BPL2PT *(volatile uint32_t*)(REG_BASE_ADDR | REGN_BPL2PTH)
293 #define REG32_BPL3PT *(volatile uint32_t*)(REG_BASE_ADDR | REGN_BPL3PTH)
294 #define REG32_BPL4PT *(volatile uint32_t*)(REG_BASE_ADDR | REGN_BPL4PTH)
295 #define REG32_BPL5PT *(volatile uint32_t*)(REG_BASE_ADDR | REGN_BPL5PTH)
296 #define REG32_BPL6PT *(volatile uint32_t*)(REG_BASE_ADDR | REGN_BPL6PTH)
297 #define REG_BPL1MOD REG(REGN_BPL1MOD)
298 #define REG_BPL2MOD REG(REGN_BPL2MOD)
299 #define REG_DIWSTART REG(REGN_DIWSTART)
300 #define REG_DIWSTOP REG(REGN_DIWSTOP)
301 #define REG_DDFSTART REG(REGN_DDFSTART)
302 #define REG_DDFSTOP REG(REGN_DDFSTOP)
303 #define REG_VPOS REG(REGN_VPOS)
304 #define REG_VPOSR REG(REGN_VPOSR)
305 #define REG_VHPOS REG(REGN_VHPOS)
306 #define REG_VHPOSR REG(REGN_VHPOSR)
307 #define REG32_VPOSR *(volatile uint32_t*)(REG_BASE_ADDR | REGN_VPOSR)
309 #define REG_COLOR_PTR ((volatile uint16_t*)(REG_BASE_ADDR | REGN_COLOR0))
310 #define REG_COLOR0 REG(REGN_COLOR0)
311 #define REG_COLOR1 REG(REGN_COLOR1)
312 #define REG_COLOR2 REG(REGN_COLOR2)
313 #define REG_COLOR3 REG(REGN_COLOR3)
314 #define REG_COLOR4 REG(REGN_COLOR4)
315 #define REG_COLOR5 REG(REGN_COLOR5)
316 #define REG_COLOR6 REG(REGN_COLOR6)
317 #define REG_COLOR7 REG(REGN_COLOR7)
318 #define REG_COLOR8 REG(REGN_COLOR8)
319 #define REG_COLOR9 REG(REGN_COLOR9)
320 #define REG_COLOR10 REG(REGN_COLOR10)
321 #define REG_COLOR11 REG(REGN_COLOR11)
322 #define REG_COLOR12 REG(REGN_COLOR12)
323 #define REG_COLOR13 REG(REGN_COLOR13)
324 #define REG_COLOR14 REG(REGN_COLOR14)
325 #define REG_COLOR15 REG(REGN_COLOR15)
326 #define REG_COLOR16 REG(REGN_COLOR16)
327 #define REG_COLOR17 REG(REGN_COLOR17)
328 #define REG_COLOR18 REG(REGN_COLOR18)
329 #define REG_COLOR19 REG(REGN_COLOR19)
330 #define REG_COLOR20 REG(REGN_COLOR20)
331 #define REG_COLOR21 REG(REGN_COLOR21)
332 #define REG_COLOR22 REG(REGN_COLOR22)
333 #define REG_COLOR23 REG(REGN_COLOR23)
334 #define REG_COLOR24 REG(REGN_COLOR24)
335 #define REG_COLOR25 REG(REGN_COLOR25)
336 #define REG_COLOR26 REG(REGN_COLOR26)
337 #define REG_COLOR27 REG(REGN_COLOR27)
338 #define REG_COLOR28 REG(REGN_COLOR28)
339 #define REG_COLOR29 REG(REGN_COLOR29)
340 #define REG_COLOR30 REG(REGN_COLOR30)
341 #define REG_COLOR31 REG(REGN_COLOR31)
343 #define REG32_COP1LC *(volatile uint32_t*)(REG_BASE_ADDR | REGN_COP1LCH)
344 #define REG32_COP2LC *(volatile uint32_t*)(REG_BASE_ADDR | REGN_COP2LCH)
345 #define REG_COPJMP1 REG(REGN_COPJMP1)
346 #define REG_COPJMP2 REG(REGN_COPJMP2)
348 #define REG_SERPER REG(REGN_SERPER)
349 #define REG_SERDATR REG(REGN_SERDATR)
350 #define REG_SERDAT REG(REGN_SERDAT)
352 /* ------ bits ------- */
353 #define SETBITS(x) ((x) | 0x8000)
354 #define CLRBITS(x) (x)
356 /* interrupt numbers */
357 enum {
358 INTR_TBE,
359 INTR_DSKBLK,
360 INTR_SOFT,
361 INTR_PORTS,
362 INTR_COPPER,
363 INTR_VERTB,
364 INTR_BLITTER,
365 INTR_AUDIO0,
366 INTR_AUDIO1,
367 INTR_AUDIO2,
368 INTR_AUDIO3,
369 INTR_RBF,
370 INTR_DSKSYN,
371 INTR_EXTER
372 };
374 /* interrupt enable flags */
375 enum {
376 INTEN_TBE = 0x0001,
377 INTEN_DSKBLK = 0x0002,
378 INTEN_SOFT = 0x0004,
379 INTEN_PORTS = 0x0008,
380 INTEN_COPPER = 0x0010,
381 INTEN_VERTB = 0x0020,
382 INTEN_BLITTER = 0x0040,
383 INTEN_AUDIO0 = 0x0080,
384 INTEN_AUDIO1 = 0x0100,
385 INTEN_AUDIO2 = 0x0200,
386 INTEN_AUDIO3 = 0x0400,
387 INTEN_RBF = 0x0800,
388 INTEN_DSKSYN = 0x1000,
389 INTEN_EXTER = 0x2000,
390 INTEN_MASTER = 0x4000,
392 INTEN_ALL = 0x7fff
393 };
395 /* DMA control flags */
396 enum {
397 DMA_AUD0 = 0x0001,
398 DMA_AUD1 = 0x0002,
399 DMA_AUD2 = 0x0004,
400 DMA_AUD3 = 0x0008,
401 DMA_AUDIO = 0x000f, /* all the above */
402 DMA_DISK = 0x0010,
403 DMA_SPRITE = 0x0020,
404 DMA_BLITTER = 0x0040,
405 DMA_COPPER = 0x0080,
406 DMA_BPL = 0x0100,
407 DMA_MASTER = 0x0200,
409 DMA_ALL = 0x01ff
410 };
412 /* Bitplane control */
413 enum {
414 BPLCON0_ERSY = 0x0002,
415 BPLCON0_LACE = 0x0004,
416 BPLCON0_LPEN = 0x0008,
417 BPLCON0_GAUD = 0x0100,
418 BPLCON0_COLOR = 0x0200,
419 BPLCON0_DBLPF = 0x0400,
420 BPLCON0_HOMOD = 0x0800,
421 BPLCON0_BPU0 = 0x1000,
422 BPLCON0_BPU1 = 0x2000,
423 BPLCON0_BPU2 = 0x4000,
424 BPLCON0_HIRES = 0x8000
425 };
427 #define BPLCON0_COUNT(x) ((x) << 12)
429 #define CIAA_PA_FIR0 0x40
430 #define CIAA_PA_FIR1 0x80
432 enum {
433 SERDATR_STOP8 = 0x0100,
434 SERDATR_STOP9 = 0x0200,
435 SERDATR_RXD = 0x0800,
436 SERDATR_TSRE = 0x1000,
437 SERDATR_TBE = 0x2000,
438 SERDATR_RBF = 0x4000,
439 SERDATR_OVRUN = 0x8000
440 };
442 #define ADKCON_UARTBRK 0x0800
444 #endif /* HWREGS_H_ */