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1 #ifndef HWREGS_H_
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2 #define HWREGS_H_
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3
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4 #include "inttypes.h"
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5
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6 #define REG_BASE_ADDR 0xdff000
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7
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8 #define REGN_BLTDDAT 0x000
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9 #define REGN_DMACONR 0x002
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10 #define REGN_VPOSR 0x004
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11 #define REGN_VHPOSR 0x006
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12 #define REGN_DSKDATR 0x008
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13 #define REGN_JOY0DAT 0x00a
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14 #define REGN_JOY1DAT 0x00c
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15 #define REGN_CLXDAT 0x00e
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16 #define REGN_ADKCONR 0x010
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17 #define REGN_POT0DAT 0x012
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18 #define REGN_POT1DAT 0x014
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19 #define REGN_POTGOR 0x016
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20 #define REGN_SERDATR 0x018
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21 #define REGN_DSKBYTR 0x01a
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22 #define REGN_INTENAR 0x01c
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23 #define REGN_INTREQR 0x01e
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24 #define REGN_DSKPTH 0x020
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25 #define REGN_DSKPTL 0x022
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26 #define REGN_DSKLEN 0x024
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27 #define REGN_DSKDAT 0x026
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28 #define REGN_REFPTR 0x028
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29 #define REGN_VPOSW 0x02a
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30 #define REGN_VHPOSW 0x02c
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31 #define REGN_COPCON 0x02e
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32 #define REGN_SERDAT 0x030
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33 #define REGN_SERPER 0x032
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34 #define REGN_POTGO 0x034
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35 #define REGN_JOYTEST 0x036
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36 #define REGN_STREQU 0x038
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37 #define REGN_STRVBL 0x03a
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38 #define REGN_STRHOR 0x03c
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39 #define REGN_STRLONG 0x03e
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40 #define REGN_BLTCON0 0x040
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41 #define REGN_BLTCON1 0x042
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42 #define REGN_BLTAFWM 0x044
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43 #define REGN_BLTALWM 0x046
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44 #define REGN_BLTCPTH 0x048
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45 #define REGN_BLTCPTL 0x04a
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46 #define REGN_BLTBPTH 0x04c
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47 #define REGN_BLTBPTL 0x04e
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48 #define REGN_BLTAPTH 0x050
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49 #define REGN_BLTAPTL 0x052
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50 #define REGN_BLTDPTH 0x054
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51 #define REGN_BLTDPTL 0x056
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52 #define REGN_BLTSIZE 0x058
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53 #define REGN_BLTCON0L 0x05a
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54 #define REGN_BLTSIZV 0x05c
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55 #define REGN_BLTSIZH 0x05e
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56 #define REGN_BLTCMOD 0x060
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57 #define REGN_BLTBMOD 0x062
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58 #define REGN_BLTAMOD 0x064
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59 #define REGN_BLTDMOD 0x066
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60 #define REGN_BLTCDAT 0x070
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61 #define REGN_BLTBDAT 0x072
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62 #define REGN_BLTADAT 0x074
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63 #define REGN_SPRHDAT 0x078
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64 #define REGN_DENISEID 0x07c
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65 #define REGN_DSKSYNC 0x07e
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66 #define REGN_COP1LCH 0x080
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67 #define REGN_COP1LCL 0x082
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68 #define REGN_COP2LCH 0x084
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69 #define REGN_COP2LCL 0x086
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70 #define REGN_CMPJMP1 0x088
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71 #define REGN_CMPJMP2 0x08a
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72 #define REGN_COPINS 0x08c
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73 #define REGN_DIWSTART 0x08e
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74 #define REGN_DIWSTOP 0x090
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75 #define REGN_DDFSTART 0x092
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76 #define REGN_DDFSTOP 0x094
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77 #define REGN_DMACON 0x096
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78 #define REGN_CLXCON 0x098
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79 #define REGN_INTENA 0x09a
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80 #define REGN_INTREQ 0x09c
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81 #define REGN_ADKCON 0x09e
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82
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83 #define REGN_AUDIO_LCH(c) (REGN_AUDIO0_BASE + (c) * 16 + 0)
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84 #define REGN_AUDIO_LCL(c) (REGN_AUDIO0_BASE + (c) * 16 + 2)
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85 #define REGN_AUDIO_LEN(c) (REGN_AUDIO0_BASE + (c) * 16 + 4)
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86 #define REGN_AUDIO_PER(c) (REGN_AUDIO0_BASE + (c) * 16 + 6)
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87 #define REGN_AUDIO_VOL(c) (REGN_AUDIO0_BASE + (c) * 16 + 8)
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88 #define REGN_AUDIO_DAT(c) (REGN_AUDIO0_BASE + (c) * 16 + 10)
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89
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90 #define REGN_AUDIO0_BASE 0x0a0
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91 #define REGN_AUD0LCH (REGN_AUDIO0_BASE + 0)
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92 #define REGN_AUD0LCL (REGN_AUDIO0_BASE + 2)
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93 #define REGN_AUD0LEN (REGN_AUDIO0_BASE + 4)
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94 #define REGN_AUD0PER (REGN_AUDIO0_BASE + 6)
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95 #define REGN_AUD0VOL (REGN_AUDIO0_BASE + 8)
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96 #define REGN_AUD0DAT (REGN_AUDIO0_BASE + 10)
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97 #define REGN_AUDIO1_BASE 0x0b0
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98 #define REGN_AUD1LCH (REGN_AUDIO1_BASE + 0)
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99 #define REGN_AUD1LCL (REGN_AUDIO1_BASE + 2)
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100 #define REGN_AUD1LEN (REGN_AUDIO1_BASE + 4)
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101 #define REGN_AUD1PER (REGN_AUDIO1_BASE + 6)
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102 #define REGN_AUD1VOL (REGN_AUDIO1_BASE + 8)
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103 #define REGN_AUD1DAT (REGN_AUDIO1_BASE + 10)
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104 #define REGN_AUDIO2_BASE 0x0c0
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105 #define REGN_AUD2LCH (REGN_AUDIO2_BASE + 0)
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106 #define REGN_AUD2LCL (REGN_AUDIO2_BASE + 2)
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107 #define REGN_AUD2LEN (REGN_AUDIO2_BASE + 4)
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108 #define REGN_AUD2PER (REGN_AUDIO2_BASE + 6)
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109 #define REGN_AUD2VOL (REGN_AUDIO2_BASE + 8)
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110 #define REGN_AUD2DAT (REGN_AUDIO2_BASE + 10)
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111 #define REGN_AUDIO3_BASE 0x0d0
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112 #define REGN_AUD3LCH (REGN_AUDIO3_BASE + 0)
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113 #define REGN_AUD3LCL (REGN_AUDIO3_BASE + 2)
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114 #define REGN_AUD3LEN (REGN_AUDIO3_BASE + 4)
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115 #define REGN_AUD3PER (REGN_AUDIO3_BASE + 6)
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116 #define REGN_AUD3VOL (REGN_AUDIO3_BASE + 8)
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117 #define REGN_AUD3DAT (REGN_AUDIO3_BASE + 10)
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118
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119 #define REGN_BPL1PTH 0x0e0
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120 #define REGN_BPL1PTL 0x0e2
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121 #define REGN_BPL2PTH 0x0e4
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122 #define REGN_BPL2PTL 0x0e6
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123 #define REGN_BPL3PTH 0x0e8
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124 #define REGN_BPL3PTL 0x0ea
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125 #define REGN_BPL4PTH 0x0ec
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126 #define REGN_BPL4PTL 0x0ee
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127 #define REGN_BPL5PTH 0x0f0
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128 #define REGN_BPL5PTL 0x0f2
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129 #define REGN_BPL6PTH 0x0f4
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130 #define REGN_BPL6PTL 0x0f6
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131 #define REGN_BPLCON0 0x100
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132 #define REGN_BPLCON1 0x102
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133 #define REGN_BPLCON2 0x104
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134 #define REGN_BPLCON3 0x106
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135 #define REGN_BPL1MOD 0x108
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136 #define REGN_BPL2MOD 0x10a
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137 #define REGN_BPL1DAT 0x110
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138 #define REGN_BPL2DAT 0x112
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139 #define REGN_BPL3DAT 0x114
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140 #define REGN_BPL4DAT 0x116
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141 #define REGN_BPL5DAT 0x118
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142 #define REGN_BPL6DAT 0x11a
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143
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144 #define REGN_SPR0PTH 0x120
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145 #define REGN_SPR0PTL 0x122
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146 #define REGN_SPR1PTH 0x124
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147 #define REGN_SPR1PTL 0x126
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148 #define REGN_SPR2PTH 0x128
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149 #define REGN_SPR2PTL 0x12a
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150 #define REGN_SPR3PTH 0x12c
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151 #define REGN_SPR3PTL 0x12e
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152 #define REGN_SPR4PTH 0x130
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153 #define REGN_SPR4PTL 0x132
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154 #define REGN_SPR5PTH 0x134
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155 #define REGN_SPR5PTL 0x136
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156 #define REGN_SPR6PTH 0x138
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157 #define REGN_SPR6PTL 0x13a
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158 #define REGN_SPR7PTH 0x13c
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159 #define REGN_SPR7PTL 0x13e
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160
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161 #define REGN_SPRITE_POS(s) (REGN_SPRITE0_BASE + (s) * 8 + 0)
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162 #define REGN_SPRITE_CTL(s) (REGN_SPRITE0_BASE + (s) * 8 + 2)
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163 #define REGN_SPRITE_DATA(s) (REGN_SPRITE0_BASE + (s) * 8 + 4)
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164 #define REGN_SPRITE_DATB(s) (REGN_SPRITE0_BASE + (s) * 8 + 6)
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165
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166 #define REGN_SPRITE0_BASE 0x140
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167 #define REGN_SPR0POS REGN_SPRITE_POS(0)
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168 #define REGN_SPR0CTL REGN_SPRITE_CTL(0)
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169 #define REGN_SPR0DATA REGN_SPRITE_DATA(0)
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170 #define REGN_SPR0DATB REGN_SPRITE_DATB(0)
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171 #define REGN_SPRITE1_BASE 0x148
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172 #define REGN_SPR1POS REGN_SPRITE_POS(1)
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173 #define REGN_SPR1CTL REGN_SPRITE_CTL(1)
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174 #define REGN_SPR1DATA REGN_SPRITE_DATA(1)
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175 #define REGN_SPR1DATB REGN_SPRITE_DATB(1)
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176 #define REGN_SPRITE2_BASE 0x150
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177 #define REGN_SPR2POS REGN_SPRITE_POS(2)
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178 #define REGN_SPR2CTL REGN_SPRITE_CTL(2)
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179 #define REGN_SPR2DATA REGN_SPRITE_DATA(2)
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180 #define REGN_SPR2DATB REGN_SPRITE_DATB(2)
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181 #define REGN_SPRITE3_BASE 0x158
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182 #define REGN_SPR3POS REGN_SPRITE_POS(3)
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183 #define REGN_SPR3CTL REGN_SPRITE_CTL(3)
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184 #define REGN_SPR3DATA REGN_SPRITE_DATA(3)
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185 #define REGN_SPR3DATB REGN_SPRITE_DATB(3)
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186 #define REGN_SPRITE4_BASE 0x160
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187 #define REGN_SPR4POS REGN_SPRITE_POS(4)
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188 #define REGN_SPR4CTL REGN_SPRITE_CTL(4)
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189 #define REGN_SPR4DATA REGN_SPRITE_DATA(4)
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190 #define REGN_SPR4DATB REGN_SPRITE_DATB(4)
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191 #define REGN_SPRITE5_BASE 0x168
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192 #define REGN_SPR5POS REGN_SPRITE_POS(5)
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193 #define REGN_SPR5CTL REGN_SPRITE_CTL(5)
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194 #define REGN_SPR5DATA REGN_SPRITE_DATA(5)
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195 #define REGN_SPR5DATB REGN_SPRITE_DATB(5)
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196 #define REGN_SPRITE6_BASE 0x170
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197 #define REGN_SPR6POS REGN_SPRITE_POS(6)
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198 #define REGN_SPR6CTL REGN_SPRITE_CTL(6)
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199 #define REGN_SPR6DATA REGN_SPRITE_DATA(6)
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200 #define REGN_SPR6DATB REGN_SPRITE_DATB(6)
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201 #define REGN_SPRITE7_BASE 0x178
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202 #define REGN_SPR7POS REGN_SPRITE_POS(7)
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203 #define REGN_SPR7CTL REGN_SPRITE_CTL(7)
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204 #define REGN_SPR7DATA REGN_SPRITE_DATA(7)
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205 #define REGN_SPR7DATB REGN_SPRITE_DATB(7)
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206
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207 #define REGN_COLOR_BASE 0x180
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208 #define REGN_COLOR(idx) (REGN_COLOR_BASE + (idx) * 2)
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209
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210 #define REGN_COLOR0 REGN_COLOR(0)
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211 #define REGN_COLOR1 REGN_COLOR(1)
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212 #define REGN_COLOR2 REGN_COLOR(2)
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213 #define REGN_COLOR3 REGN_COLOR(3)
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214 #define REGN_COLOR4 REGN_COLOR(4)
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215 #define REGN_COLOR5 REGN_COLOR(5)
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216 #define REGN_COLOR6 REGN_COLOR(6)
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217 #define REGN_COLOR7 REGN_COLOR(7)
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218 #define REGN_COLOR8 REGN_COLOR(8)
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219 #define REGN_COLOR9 REGN_COLOR(9)
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220 #define REGN_COLOR10 REGN_COLOR(10)
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221 #define REGN_COLOR11 REGN_COLOR(11)
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222 #define REGN_COLOR12 REGN_COLOR(12)
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223 #define REGN_COLOR13 REGN_COLOR(13)
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224 #define REGN_COLOR14 REGN_COLOR(14)
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225 #define REGN_COLOR15 REGN_COLOR(15)
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226 #define REGN_COLOR16 REGN_COLOR(16)
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227 #define REGN_COLOR17 REGN_COLOR(17)
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228 #define REGN_COLOR18 REGN_COLOR(18)
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229 #define REGN_COLOR19 REGN_COLOR(19)
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230 #define REGN_COLOR20 REGN_COLOR(20)
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231 #define REGN_COLOR21 REGN_COLOR(21)
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232 #define REGN_COLOR22 REGN_COLOR(22)
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233 #define REGN_COLOR23 REGN_COLOR(23)
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234 #define REGN_COLOR24 REGN_COLOR(24)
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235 #define REGN_COLOR25 REGN_COLOR(25)
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236 #define REGN_COLOR26 REGN_COLOR(26)
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237 #define REGN_COLOR27 REGN_COLOR(27)
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238 #define REGN_COLOR28 REGN_COLOR(28)
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239 #define REGN_COLOR29 REGN_COLOR(29)
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240 #define REGN_COLOR30 REGN_COLOR(30)
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241 #define REGN_COLOR31 REGN_COLOR(31)
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242
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243 #define REGN_HTOTAL 0x1c0
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244 #define REGN_HSSTOP 0x1c2
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245 #define REGN_HBSTART 0x1c4
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246 #define REGN_HBSTOP 0x1c6
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247 #define REGN_VTOTAL 0x1c8
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248 #define REGN_VSSTOP 0x1ca
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249 #define REGN_VBSTART 0x1cc
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250 #define REGN_VBSTOP 0x1ce
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251 #define REGN_BEAMCON0 0x1dc
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252 #define REGN_HSSTART 0x1de
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253 #define REGN_VSSTART 0x1e0
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254 #define REGN_HCENTER 0x1e2
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255 #define REGN_DIWHIGH 0x1e4
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256
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257 #define REGN_COP1LCH 0x080
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258 #define REGN_COP1LCL 0x082
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259 #define REGN_COP2LCH 0x084
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260 #define REGN_COP2LCL 0x086
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261 #define REGN_COPJMP1 0x088
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262 #define REGN_COPJMP2 0x08a
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263
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264 #define REG(r) (*(volatile uint16_t*)(REG_BASE_ADDR | (r)))
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265
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266 #define REG_CIAA_PORTA *(volatile uint8_t*)0xbfe001
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267
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268 #define REG_INTENA REG(REGN_INTENA)
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269 #define REG_INTENAR REG(REGN_INTENAR)
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270 #define REG_INTREQ REG(REGN_INTREQ)
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271 #define REG_INTREQR REG(REGN_INTREQR)
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272 #define REG_ADKCON REG(REGN_ADKCON)
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273 #define REG_ADKCONR REG(REGN_ADKCONR)
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274 #define REG_DMACON REG(REGN_DMACON)
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275 #define REG_DMACONR REG(REGN_DMACONR)
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276 #define REG_BPLCON0 REG(REGN_BPLCON0)
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277 #define REG_BPLCON1 REG(REGN_BPLCON1)
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278 #define REG_BPLCON2 REG(REGN_BPLCON2)
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279 #define REG_BPL1PTH REG(REGN_BPL1PTH)
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280 #define REG_BPL2PTH REG(REGN_BPL2PTH)
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281 #define REG_BPL3PTH REG(REGN_BPL3PTH)
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282 #define REG_BPL4PTH REG(REGN_BPL4PTH)
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283 #define REG_BPL5PTH REG(REGN_BPL5PTH)
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284 #define REG_BPL6PTH REG(REGN_BPL6PTH)
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285 #define REG_BPL1PTL REG(REGN_BPL1PTL)
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286 #define REG_BPL2PTL REG(REGN_BPL2PTL)
|
nuclear@1
|
287 #define REG_BPL3PTL REG(REGN_BPL3PTL)
|
nuclear@1
|
288 #define REG_BPL4PTL REG(REGN_BPL4PTL)
|
nuclear@1
|
289 #define REG_BPL5PTL REG(REGN_BPL5PTL)
|
nuclear@1
|
290 #define REG_BPL6PTL REG(REGN_BPL6PTL)
|
nuclear@1
|
291 #define REG32_BPL1PT *(volatile uint32_t*)(REG_BASE_ADDR | REGN_BPL1PTH)
|
nuclear@1
|
292 #define REG32_BPL2PT *(volatile uint32_t*)(REG_BASE_ADDR | REGN_BPL2PTH)
|
nuclear@1
|
293 #define REG32_BPL3PT *(volatile uint32_t*)(REG_BASE_ADDR | REGN_BPL3PTH)
|
nuclear@1
|
294 #define REG32_BPL4PT *(volatile uint32_t*)(REG_BASE_ADDR | REGN_BPL4PTH)
|
nuclear@1
|
295 #define REG32_BPL5PT *(volatile uint32_t*)(REG_BASE_ADDR | REGN_BPL5PTH)
|
nuclear@1
|
296 #define REG32_BPL6PT *(volatile uint32_t*)(REG_BASE_ADDR | REGN_BPL6PTH)
|
nuclear@1
|
297 #define REG_BPL1MOD REG(REGN_BPL1MOD)
|
nuclear@1
|
298 #define REG_BPL2MOD REG(REGN_BPL2MOD)
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nuclear@1
|
299 #define REG_DIWSTART REG(REGN_DIWSTART)
|
nuclear@1
|
300 #define REG_DIWSTOP REG(REGN_DIWSTOP)
|
nuclear@1
|
301 #define REG_DDFSTART REG(REGN_DDFSTART)
|
nuclear@1
|
302 #define REG_DDFSTOP REG(REGN_DDFSTOP)
|
nuclear@1
|
303 #define REG_VPOS REG(REGN_VPOS)
|
nuclear@1
|
304 #define REG_VPOSR REG(REGN_VPOSR)
|
nuclear@1
|
305 #define REG_VHPOS REG(REGN_VHPOS)
|
nuclear@1
|
306 #define REG_VHPOSR REG(REGN_VHPOSR)
|
nuclear@1
|
307 #define REG32_VPOSR *(volatile uint32_t*)(REG_BASE_ADDR | REGN_VPOSR)
|
nuclear@1
|
308
|
nuclear@1
|
309 #define REG_COLOR_PTR ((volatile uint16_t*)(REG_BASE_ADDR | REGN_COLOR0))
|
nuclear@1
|
310 #define REG_COLOR0 REG(REGN_COLOR0)
|
nuclear@1
|
311 #define REG_COLOR1 REG(REGN_COLOR1)
|
nuclear@1
|
312 #define REG_COLOR2 REG(REGN_COLOR2)
|
nuclear@1
|
313 #define REG_COLOR3 REG(REGN_COLOR3)
|
nuclear@1
|
314 #define REG_COLOR4 REG(REGN_COLOR4)
|
nuclear@1
|
315 #define REG_COLOR5 REG(REGN_COLOR5)
|
nuclear@1
|
316 #define REG_COLOR6 REG(REGN_COLOR6)
|
nuclear@1
|
317 #define REG_COLOR7 REG(REGN_COLOR7)
|
nuclear@1
|
318 #define REG_COLOR8 REG(REGN_COLOR8)
|
nuclear@1
|
319 #define REG_COLOR9 REG(REGN_COLOR9)
|
nuclear@1
|
320 #define REG_COLOR10 REG(REGN_COLOR10)
|
nuclear@1
|
321 #define REG_COLOR11 REG(REGN_COLOR11)
|
nuclear@1
|
322 #define REG_COLOR12 REG(REGN_COLOR12)
|
nuclear@1
|
323 #define REG_COLOR13 REG(REGN_COLOR13)
|
nuclear@1
|
324 #define REG_COLOR14 REG(REGN_COLOR14)
|
nuclear@1
|
325 #define REG_COLOR15 REG(REGN_COLOR15)
|
nuclear@1
|
326 #define REG_COLOR16 REG(REGN_COLOR16)
|
nuclear@1
|
327 #define REG_COLOR17 REG(REGN_COLOR17)
|
nuclear@1
|
328 #define REG_COLOR18 REG(REGN_COLOR18)
|
nuclear@1
|
329 #define REG_COLOR19 REG(REGN_COLOR19)
|
nuclear@1
|
330 #define REG_COLOR20 REG(REGN_COLOR20)
|
nuclear@1
|
331 #define REG_COLOR21 REG(REGN_COLOR21)
|
nuclear@1
|
332 #define REG_COLOR22 REG(REGN_COLOR22)
|
nuclear@1
|
333 #define REG_COLOR23 REG(REGN_COLOR23)
|
nuclear@1
|
334 #define REG_COLOR24 REG(REGN_COLOR24)
|
nuclear@1
|
335 #define REG_COLOR25 REG(REGN_COLOR25)
|
nuclear@1
|
336 #define REG_COLOR26 REG(REGN_COLOR26)
|
nuclear@1
|
337 #define REG_COLOR27 REG(REGN_COLOR27)
|
nuclear@1
|
338 #define REG_COLOR28 REG(REGN_COLOR28)
|
nuclear@1
|
339 #define REG_COLOR29 REG(REGN_COLOR29)
|
nuclear@1
|
340 #define REG_COLOR30 REG(REGN_COLOR30)
|
nuclear@1
|
341 #define REG_COLOR31 REG(REGN_COLOR31)
|
nuclear@1
|
342
|
nuclear@1
|
343 #define REG32_COP1LC *(volatile uint32_t*)(REG_BASE_ADDR | REGN_COP1LCH)
|
nuclear@1
|
344 #define REG32_COP2LC *(volatile uint32_t*)(REG_BASE_ADDR | REGN_COP2LCH)
|
nuclear@1
|
345 #define REG_COPJMP1 REG(REGN_COPJMP1)
|
nuclear@1
|
346 #define REG_COPJMP2 REG(REGN_COPJMP2)
|
nuclear@1
|
347
|
nuclear@4
|
348 #define REG_SERPER REG(REGN_SERPER)
|
nuclear@4
|
349 #define REG_SERDATR REG(REGN_SERDATR)
|
nuclear@4
|
350 #define REG_SERDAT REG(REGN_SERDAT)
|
nuclear@4
|
351
|
nuclear@1
|
352 /* ------ bits ------- */
|
nuclear@1
|
353 #define SETBITS(x) ((x) | 0x8000)
|
nuclear@1
|
354 #define CLRBITS(x) (x)
|
nuclear@1
|
355
|
nuclear@1
|
356 /* interrupt numbers */
|
nuclear@1
|
357 enum {
|
nuclear@1
|
358 INTR_TBE,
|
nuclear@1
|
359 INTR_DSKBLK,
|
nuclear@1
|
360 INTR_SOFT,
|
nuclear@1
|
361 INTR_PORTS,
|
nuclear@1
|
362 INTR_COPPER,
|
nuclear@1
|
363 INTR_VERTB,
|
nuclear@1
|
364 INTR_BLITTER,
|
nuclear@1
|
365 INTR_AUDIO0,
|
nuclear@1
|
366 INTR_AUDIO1,
|
nuclear@1
|
367 INTR_AUDIO2,
|
nuclear@1
|
368 INTR_AUDIO3,
|
nuclear@1
|
369 INTR_RBF,
|
nuclear@1
|
370 INTR_DSKSYN,
|
nuclear@1
|
371 INTR_EXTER
|
nuclear@1
|
372 };
|
nuclear@1
|
373
|
nuclear@1
|
374 /* interrupt enable flags */
|
nuclear@1
|
375 enum {
|
nuclear@1
|
376 INTEN_TBE = 0x0001,
|
nuclear@1
|
377 INTEN_DSKBLK = 0x0002,
|
nuclear@1
|
378 INTEN_SOFT = 0x0004,
|
nuclear@1
|
379 INTEN_PORTS = 0x0008,
|
nuclear@1
|
380 INTEN_COPPER = 0x0010,
|
nuclear@1
|
381 INTEN_VERTB = 0x0020,
|
nuclear@1
|
382 INTEN_BLITTER = 0x0040,
|
nuclear@1
|
383 INTEN_AUDIO0 = 0x0080,
|
nuclear@1
|
384 INTEN_AUDIO1 = 0x0100,
|
nuclear@1
|
385 INTEN_AUDIO2 = 0x0200,
|
nuclear@1
|
386 INTEN_AUDIO3 = 0x0400,
|
nuclear@1
|
387 INTEN_RBF = 0x0800,
|
nuclear@1
|
388 INTEN_DSKSYN = 0x1000,
|
nuclear@1
|
389 INTEN_EXTER = 0x2000,
|
nuclear@1
|
390 INTEN_MASTER = 0x4000,
|
nuclear@1
|
391
|
nuclear@1
|
392 INTEN_ALL = 0x7fff
|
nuclear@1
|
393 };
|
nuclear@1
|
394
|
nuclear@1
|
395 /* DMA control flags */
|
nuclear@1
|
396 enum {
|
nuclear@1
|
397 DMA_AUD0 = 0x0001,
|
nuclear@1
|
398 DMA_AUD1 = 0x0002,
|
nuclear@1
|
399 DMA_AUD2 = 0x0004,
|
nuclear@1
|
400 DMA_AUD3 = 0x0008,
|
nuclear@1
|
401 DMA_AUDIO = 0x000f, /* all the above */
|
nuclear@1
|
402 DMA_DISK = 0x0010,
|
nuclear@1
|
403 DMA_SPRITE = 0x0020,
|
nuclear@1
|
404 DMA_BLITTER = 0x0040,
|
nuclear@1
|
405 DMA_COPPER = 0x0080,
|
nuclear@1
|
406 DMA_BPL = 0x0100,
|
nuclear@1
|
407 DMA_MASTER = 0x0200,
|
nuclear@1
|
408
|
nuclear@1
|
409 DMA_ALL = 0x01ff
|
nuclear@1
|
410 };
|
nuclear@1
|
411
|
nuclear@1
|
412 /* Bitplane control */
|
nuclear@1
|
413 enum {
|
nuclear@1
|
414 BPLCON0_ERSY = 0x0002,
|
nuclear@1
|
415 BPLCON0_LACE = 0x0004,
|
nuclear@1
|
416 BPLCON0_LPEN = 0x0008,
|
nuclear@1
|
417 BPLCON0_GAUD = 0x0100,
|
nuclear@1
|
418 BPLCON0_COLOR = 0x0200,
|
nuclear@1
|
419 BPLCON0_DBLPF = 0x0400,
|
nuclear@1
|
420 BPLCON0_HOMOD = 0x0800,
|
nuclear@1
|
421 BPLCON0_BPU0 = 0x1000,
|
nuclear@1
|
422 BPLCON0_BPU1 = 0x2000,
|
nuclear@1
|
423 BPLCON0_BPU2 = 0x4000,
|
nuclear@1
|
424 BPLCON0_HIRES = 0x8000
|
nuclear@1
|
425 };
|
nuclear@1
|
426
|
nuclear@1
|
427 #define BPLCON0_COUNT(x) ((x) << 12)
|
nuclear@1
|
428
|
nuclear@1
|
429 #define CIAA_PA_FIR0 0x40
|
nuclear@1
|
430 #define CIAA_PA_FIR1 0x80
|
nuclear@1
|
431
|
nuclear@4
|
432 enum {
|
nuclear@4
|
433 SERDATR_STOP8 = 0x0100,
|
nuclear@4
|
434 SERDATR_STOP9 = 0x0200,
|
nuclear@4
|
435 SERDATR_RXD = 0x0800,
|
nuclear@4
|
436 SERDATR_TSRE = 0x1000,
|
nuclear@4
|
437 SERDATR_TBE = 0x2000,
|
nuclear@4
|
438 SERDATR_RBF = 0x4000,
|
nuclear@4
|
439 SERDATR_OVRUN = 0x8000
|
nuclear@4
|
440 };
|
nuclear@4
|
441
|
nuclear@4
|
442 #define ADKCON_UARTBRK 0x0800
|
nuclear@4
|
443
|
nuclear@1
|
444 #endif /* HWREGS_H_ */
|