by John Tsiombikas
It's a well known fact that many older computers and game consoles, being designed to output on a television set, exhibit differences between US models which work with NTSC TVs, and european models which work with PAL TVs.
The interesting thing about the SEGA Mega Drive in particular (or Genesis as it was called in the US), is that the hardware designers at SEGA really thought this PAL/NTSC thing through, and made sure to support both with the exact same hardware. The Mega Drive Video Display Processor (VDP) chip, can work either in PAL 50Hz mode, or in NTSC 60Hz mode, selectable by a set of jumper links on the board. The only minor difference in the hardware, is the main crystal oscillator frequency. PAL models use a 53.203Mhz oscillator, which is divided by 7 to generate a ~7.6004MHz CPU clock, and by 12 to get 4.433583Mhz which is close enough to the PAL chroma subcarrier frequency. NTSC models on the other hand use a 53.6931Mhz oscillator, which is divided by 7 to generate a ~7.6704MHz CPU clock, and by 15 to get 3.57954Mhz for the NTSC chroma subcarrier.
After learning how pronounced the difference is when running programs written for the NTSC Mega Drive on a PAL Mega Drive, I decided to at the very least solder a couple of pin headers on the board to switch between the two modes and see the difference for myself.
Changing the bottom jumper to the NTSC position indeed works, and makes the Mega Drive run at 60Hz. The only problem is that the picture on the TV is black & white. Now that I think about it, it was lucky that my TV managed to work at all with an NTSC signal. It shouldn't necessarily be the case, as it's a proper analogue CRT TV. I must investigate further at some point.
It's important to realize that when switching the VDP of a PAL Mega Drive to NTSC mode, it changes the clock divider for the chroma subcarrier from 12 to 15, because it expects a 53.6931MHz clock signal. The oscillator however didn't change, it's still the 53.203MHz oscillator of my PAL model. This results in the chroma subcarrier frequency produced by the VDP, and fed to the CXA1145 video encoder IC, being the wrong frequency (namely 3.5369MHz). Since the output video signal has an invalid chroma subcarrier, the television can't recognize it, falling back to a black & white picture.
To fix this issue I followed the advice of this excellent article by static-void with a few minor alterations. The gist of it is to cut the trace taking the chroma subcarrier signal from the VDP to the video encoder, and inject our own clock signal which is always (close to) 4.43MHz, irrespective of whether the VDP is in PAL or NTSC mode. The (in retrospect obvious) way to produce this clock signal, is to do exactly the same division by 12 of the main clock, as the VDP would do in PAL mode.
I used a couple 74hc74 chips instead of the 74act175 proposed by the author of the article, because that's what I had in my part bin. It's marginal in terms of response speed, but it works. The datasheet of the 74hc74 from texas instruments states a required minimum pulse duration of 19ns, while at 53.203MHz the clock pulses driving my flip-flops are 18.8ns long.
Having constructed the clock divider, I needed to figure out where to get the main clock signal, which track to cut, and where to feed my own clock. The photos provided by the author of his own modification where of a model 2 mega drive board, which is quite different from the model 1 I have.
The input signal was easy to locate by probing a few points around the oscillator. I found a nice 5v peak-to-peak 53.203MHz square wave at a pad of a ferrite bead.
To find where to feed the new signal checked the datasheet of the CXA1145 video encoder chip. Initially I thought about connecting my signal to chroma oscillator input pin (pin 6) of that chip directly, but after probing it I saw a smoothed version of the chroma clock, just 1v peak-to-peak, so it probably won't like my 5v square wave very much.
Going back to the pictures in the article, the author used one end of resistor R61 to feed the signal, so I set out to find, with the help of the model 2 schematic which I did find on the web, the corresponding point in the model 1 board. By following the tracks backwards from pin 6 of the CXA1145 chip, I found the capacitor which AC-couples the clock signal to that pin, connected to a series resistor just like R61 in the schematic.
I probed that point, and indeed I found a nice 5v ~4.43MHz square wave there.
So I connected one end of a long
antenna wire to bring it over
to the front side of the board where I intended to mount my clock divider.
For the power and ground connections, I used a convenient nearby bypass capacitor. I thought about sticking my board on top of the VDP with double-sided tape, but I decided to leave it just floating over it instead, to avoid obstructing the convection airflow over the VDP. At this point I also soldered a switch to a long 3-lane ribbon cable with a connector at the other end, to plug on my pin-headers in place of the jumper.
And here is the switch mounted at the back of my mega drive, after putting everything together.